Changeset ef1a3a8 in mainline for uspace/drv/bus/usb/xhci/endpoint.h

Timestamp:

2017-10-29T11:53:45Z (8 years ago)

Author:

Petr Manek <petr.manek@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

a312d8f

Parents:

d33dc780

Message:

Added memory structure for stream TRB rings. Implemented their initialization. Fixed white space.

File:

• uspace/drv/bus/usb/xhci/endpoint.h (modified) (1 diff)

uspace/drv/bus/usb/xhci/endpoint.h

@@ -74 +74 @@
         xhci_transfer_t active_transfer;
 
-        /** Primary stream context array (or NULL if endpoint doesn't use streams) */
+        /** Primary stream context array (or NULL if endpoint doesn't use streams). */
         xhci_stream_ctx_t *primary_stream_ctx_array;
 
-        /** Size of the allocated primary stream context array. */
+        /** Primary stream ring array (or NULL if endpoint doesn't use streams). */
+        xhci_trb_ring_t *primary_stream_rings;
+
+        /** Size of the allocated primary stream context array (and ring array). */
         uint16_t primary_stream_ctx_array_size;