Changeset e25eca80 in mainline for kernel/arch/ia64/include/barrier.h


Ignore:
Timestamp:
2008-06-13T20:36:38Z (17 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
d5087aa
Parents:
80dabb8d
Message:

Add smc_coherence() macro to all architectures.
So far, only amd64, ia32, ia64 and sparc64 are implemented.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/ia64/include/barrier.h

    r80dabb8d re25eca80  
    4646#define write_barrier()         memory_barrier()
    4747
    48 #define srlz_i()                asm volatile (";; srlz.i ;;\n" ::: "memory")
    49 #define srlz_d()                asm volatile (";; srlz.d\n" ::: "memory")
     48#define srlz_i()                \
     49        asm volatile (";; srlz.i ;;\n" ::: "memory")
     50#define srlz_d()                \
     51        asm volatile (";; srlz.d\n" ::: "memory")
     52
     53#define fc_i(a)                 \
     54        asm volatile ("fc.i %0\n" : "r" ((a)) :: "memory") 
     55#define sync_i()                \
     56        asm volatile (";; sync.i\n" ::: "memory")
     57
     58#define smc_coherence(a)        \
     59{                               \
     60        fc_i((a));              \
     61        sync_i();               \
     62        srlz_i();               \
     63}
    5064
    5165#endif
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