Changeset a03b609 in mainline

Timestamp:

2013-01-19T18:17:27Z (12 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

26e3db2

Parents:

827aae5

Message:

arm32: Convert sctlr use to cp15 helpers.

Location:

kernel/arch/arm32

Files:

• include/cp15.h (modified) (1 diff)
• include/regutils.h (modified) (1 diff)
• src/cpu/cpu.c (modified) (4 diffs)
• src/exception.c (modified) (2 diffs)

kernel/arch/arm32/include/cp15.h

@@ -149 +149 @@
 
 /* System control registers */
+/* COntrol register bit values see ch. B4.1.130 of ARM Architecture Reference
+ * Manual ARMv7-A and ARMv7-R edition, page 1687 */
+enum {
+        SCTLR_MMU_EN_FLAG            = 1 << 0,
+        SCTLR_ALIGN_CHECK_EN_FLAG    = 1 << 1,  /* Allow alignemnt check */
+        SCTLR_CACHE_EN_FLAG          = 1 << 2,
+        SCTLR_CP15_BARRIER_EN_FLAG   = 1 << 5,
+        SCTLR_B_EN_FLAG              = 1 << 7,  /* ARMv6-, big endian switch */
+        SCTLR_SWAP_EN_FLAG           = 1 << 10,
+        SCTLR_BRANCH_PREDICT_EN_FLAG = 1 << 11,
+        SCTLR_INST_CACHE_EN_FLAG     = 1 << 12,
+        SCTLR_HIGH_VECTORS_EN_FLAG   = 1 << 13,
+        SCTLR_ROUND_ROBIN_EN_FLAG    = 1 << 14,
+        SCTLR_HW_ACCESS_FLAG_EN_FLAG = 1 << 17,
+        SCTLR_WRITE_XN_EN_FLAG       = 1 << 19, /* Only if virt. supported */
+        SCTLR_USPCE_WRITE_XN_EN_FLAG = 1 << 20, /* Only if virt. supported */
+        SCTLR_FAST_IRQ_EN_FLAG       = 1 << 21, /* Disable impl. specific feat*/
+        SCTLR_UNALIGNED_EN_FLAG      = 1 << 22, /* Must be 1 on armv7 */
+        SCTLR_IRQ_VECTORS_EN_FLAG    = 1 << 24,
+        SCTLR_BIG_ENDIAN_EXC_FLAG    = 1 << 25,
+        SCTLR_NMFI_EN_FLAG           = 1 << 27,
+        SCTLR_TEX_REMAP_EN_FLAG      = 1 << 28,
+        SCTLR_ACCESS_FLAG_EN_FLAG    = 1 << 29,
+        SCTLR_THUMB_EXC_EN_FLAG      = 1 << 30,
+};
 CONTROL_REG_GEN_READ(SCTLR, c1, 0, c0, 0);
 CONTROL_REG_GEN_WRITE(SCTLR, c1, 0, c0, 0);

kernel/arch/arm32/include/regutils.h

@@ -40 +40 @@
 #define STATUS_REG_IRQ_DISABLED_BIT  (1 << 7)
 #define STATUS_REG_MODE_MASK         0x1f
-
-/* COntrol register bit values see ch. B4.1.130 of ARM Architecture Reference
- * Manual ARMv7-A and ARMv7-R edition, page 1687 */
-#define CP15_R1_MMU_EN            (1 << 0)
-#define CP15_R1_ALIGN_CHECK_EN    (1 << 1)  /* Allow alignemnt check */
-#define CP15_R1_CACHE_EN          (1 << 2)
-#define CP15_R1_CP15_BARRIER_EN   (1 << 5)
-#define CP15_R1_B_EN              (1 << 7)  /* ARMv6- only, big endian switch */
-#define CP15_R1_SWAP_EN           (1 << 10)
-#define CP15_R1_BRANCH_PREDICT_EN (1 << 11)
-#define CP15_R1_INST_CACHE_EN     (1 << 12)
-#define CP15_R1_HIGH_VECTORS_EN   (1 << 13)
-#define CP15_R1_ROUND_ROBIN_EN    (1 << 14)
-#define CP15_R1_HW_ACCESS_FLAG_EN (1 << 17)
-#define CP15_R1_WRITE_XN_EN       (1 << 19) /* Only if virt. supported */
-#define CP15_R1_USPCE_WRITE_XN_EN (1 << 20) /* Only if virt. supported */
-#define CP15_R1_FAST_IRQ_EN       (1 << 21) /* Disbale impl.specific features */
-#define CP15_R1_UNALIGNED_EN      (1 << 22) /* Must be 1 on armv7 */
-#define CP15_R1_IRQ_VECTORS_EN    (1 << 24)
-#define CP15_R1_BIG_ENDIAN_EXC    (1 << 25)
-#define CP15_R1_NMFI_EN           (1 << 27)
-#define CP15_R1_TEX_REMAP_EN      (1 << 28)
-#define CP15_R1_ACCESS_FLAG_EN    (1 << 29)
-#define CP15_R1_THUMB_EXC_EN      (1 << 30)
 
 /* ARM Processor Operation Modes */

kernel/arch/arm32/src/cpu/cpu.c

@@ -129 +129 @@
 void cpu_arch_init(void)
 {
-        /* Get rid of any boot code hiding in ICache
-         * This is safe without regards to ICache state. */
-        memory_barrier();
-        smc_coherence();
-
-        uint32_t control_reg = 0;
-        asm volatile (
-                "mrc p15, 0, %[control_reg], c1, c0"
-                : [control_reg] "=r" (control_reg)
-        );
+        uint32_t control_reg = SCTLR_read();
         
         /* Turn off tex remap, RAZ/WI prior to armv7 */
-        control_reg &= ~CP15_R1_TEX_REMAP_EN;
+        control_reg &= ~SCTLR_TEX_REMAP_EN_FLAG;
         /* Turn off accessed flag, RAZ/WI prior to armv7 */
-        control_reg &= ~(CP15_R1_ACCESS_FLAG_EN | CP15_R1_HW_ACCESS_FLAG_EN);
+        control_reg &= ~(SCTLR_ACCESS_FLAG_EN_FLAG | SCTLR_HW_ACCESS_FLAG_EN_FLAG);
         /* Disable branch prediction RAZ/WI if not supported */
-        control_reg &= ~CP15_R1_BRANCH_PREDICT_EN;
+        control_reg &= ~SCTLR_BRANCH_PREDICT_EN_FLAG;
 
         /* Unaligned access is supported on armv6+ */
@@ -153 +144 @@
          * see ARM Architecture Reference Manual ARMv7-A and ARMv7-R edition
          * L.3.1 (p. 2456) */
-        control_reg |= CP15_R1_UNALIGNED_EN;
+        control_reg |= SCTLR_UNALIGNED_EN_FLAG;
         /* Disable alignment checks, this turns unaligned access to undefined,
          * unless U bit is set. */
-        control_reg &= ~CP15_R1_ALIGN_CHECK_EN;
+        control_reg &= ~SCTLR_ALIGN_CHECK_EN_FLAG;
         /* Enable caching, On arm prior to armv7 there is only one level
          * of caches. Data cache is coherent.
@@ -167 +158 @@
          * L2 Cache for armv7 was enabled in boot code.
          */
-        control_reg |= CP15_R1_CACHE_EN;
+        control_reg |= SCTLR_CACHE_EN_FLAG;
 #endif
 #ifdef PROCESSOR_cortex_a8
@@ -173 +164 @@
           * Cortex-A8 implements IVIPT extension.
           * Cortex-A8 TRM ch. 7.2.6 p. 7-4 (PDF 245) */
-        control_reg |= CP15_R1_INST_CACHE_EN;
-#endif
-        
-        asm volatile (
-                "mcr p15, 0, %[control_reg], c1, c0"
-                :: [control_reg] "r" (control_reg)
-        );
+        control_reg |= SCTLR_INST_CACHE_EN_FLAG;
+#endif
+        SCTLR_write(control_reg);
+
 #ifdef CONFIG_FPU
         fpu_setup();

kernel/arch/arm32/src/exception.c

@@ -39 +39 @@
 #include <interrupt.h>
 #include <arch/mm/page_fault.h>
+#include <arch/cp15.h>
 #include <arch/barrier.h>
 #include <print.h>
@@ -136 +137 @@
 static void high_vectors(void)
 {
-        uint32_t control_reg = 0;
-        asm volatile (
-                "mrc p15, 0, %[control_reg], c1, c0"
-                : [control_reg] "=r" (control_reg)
-        );
+        uint32_t control_reg = SCTLR_read();
         
         /* switch on the high vectors bit */
-        control_reg |= CP15_R1_HIGH_VECTORS_EN;
-        
-        asm volatile (
-                "mcr p15, 0, %[control_reg], c1, c0"
-                :: [control_reg] "r" (control_reg)
-        );
+        control_reg |= SCTLR_HIGH_VECTORS_EN_FLAG;
+        
+        SCTLR_write(control_reg);
 }
 #endif