Changeset 725d038 in mainline
- Timestamp:
- 2012-07-05T20:23:28Z (12 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 4bec78f
- Parents:
- 7ca22e5 (diff), 5e4f22b (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the(diff)
links above to see all the changes relative to each parent. - Location:
- kernel
- Files:
-
- 15 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/abs32le/include/mm/page.h
r7ca22e5 r725d038 105 105 set_pt_flags((pte_t *) (ptl3), (size_t) (i), (x)) 106 106 107 /* Set PTE present bit accessors for each level. */ 108 #define SET_PTL1_PRESENT_ARCH(ptl0, i) \ 109 set_pt_present((pte_t *) (ptl0), (size_t) (i)) 110 #define SET_PTL2_PRESENT_ARCH(ptl1, i) 111 #define SET_PTL3_PRESENT_ARCH(ptl2, i) 112 #define SET_FRAME_PRESENT_ARCH(ptl3, i) \ 113 set_pt_present((pte_t *) (ptl3), (size_t) (i)) 114 107 115 /* Macros for querying the last level entries. */ 108 116 #define PTE_VALID_ARCH(p) \ … … 173 181 } 174 182 183 NO_TRACE static inline void set_pt_present(pte_t *pt, size_t i) 184 WRITES(ARRAY_RANGE(pt, PTL0_ENTRIES_ARCH)) 185 REQUIRES_ARRAY_MUTABLE(pt, PTL0_ENTRIES_ARCH) 186 { 187 pte_t *p = &pt[i]; 188 189 p->present = 1; 190 } 191 175 192 extern void page_arch_init(void); 176 193 extern void page_fault(unsigned int, istate_t *); -
kernel/arch/amd64/include/mm/page.h
r7ca22e5 r725d038 119 119 set_pt_flags((pte_t *) (ptl3), (size_t) (i), (x)) 120 120 121 /* Set PTE present bit accessors for each level. */ 122 #define SET_PTL1_PRESENT_ARCH(ptl0, i) \ 123 set_pt_present((pte_t *) (ptl0), (size_t) (i)) 124 #define SET_PTL2_PRESENT_ARCH(ptl1, i) \ 125 set_pt_present((pte_t *) (ptl1), (size_t) (i)) 126 #define SET_PTL3_PRESENT_ARCH(ptl2, i) \ 127 set_pt_present((pte_t *) (ptl2), (size_t) (i)) 128 #define SET_FRAME_PRESENT_ARCH(ptl3, i) \ 129 set_pt_present((pte_t *) (ptl3), (size_t) (i)) 130 121 131 /* Macros for querying the last-level PTE entries. */ 122 132 #define PTE_VALID_ARCH(p) \ … … 215 225 } 216 226 227 NO_TRACE static inline void set_pt_present(pte_t *pt, size_t i) 228 { 229 pte_t *p = &pt[i]; 230 231 p->present = 1; 232 } 233 217 234 extern void page_arch_init(void); 218 235 extern void page_fault(unsigned int, istate_t *); -
kernel/arch/amd64/src/mm/page.c
r7ca22e5 r725d038 57 57 uintptr_t cur; 58 58 unsigned int identity_flags = 59 PAGE_ CACHEABLE | PAGE_EXEC | PAGE_GLOBAL | PAGE_WRITE;59 PAGE_GLOBAL | PAGE_CACHEABLE | PAGE_EXEC | PAGE_WRITE | PAGE_READ; 60 60 61 61 page_mapping_operations = &pt_mapping_operations; -
kernel/arch/arm32/include/mm/page.h
r7ca22e5 r725d038 40 40 #include <mm/mm.h> 41 41 #include <arch/exception.h> 42 #include <arch/barrier.h> 42 43 #include <trace.h> 43 44 … … 109 110 #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \ 110 111 set_pt_level1_flags((pte_t *) (ptl3), (size_t) (i), (x)) 112 113 /* Set PTE present bit accessors for each level. */ 114 #define SET_PTL1_PRESENT_ARCH(ptl0, i) \ 115 set_pt_level0_present((pte_t *) (ptl0), (size_t) (i)) 116 #define SET_PTL2_PRESENT_ARCH(ptl1, i) 117 #define SET_PTL3_PRESENT_ARCH(ptl2, i) 118 #define SET_FRAME_PRESENT_ARCH(ptl3, i) \ 119 set_pt_level1_present((pte_t *) (ptl3), (size_t) (i)) 111 120 112 121 /* Macros for querying the last-level PTE entries. */ … … 267 276 } 268 277 278 NO_TRACE static inline void set_pt_level0_present(pte_t *pt, size_t i) 279 { 280 pte_level0_t *p = &pt[i].l0; 281 282 p->should_be_zero = 0; 283 write_barrier(); 284 p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE; 285 } 269 286 270 287 /** Sets flags of level 1 page table entry. … … 283 300 pte_level1_t *p = &pt[i].l1; 284 301 285 if (flags & PAGE_NOT_PRESENT) {302 if (flags & PAGE_NOT_PRESENT) 286 303 p->descriptor_type = PTE_DESCRIPTOR_NOT_PRESENT; 287 p->access_permission_3 = 1; 288 } else { 304 else 289 305 p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; 290 p->access_permission_3 = p->access_permission_0;291 }292 306 293 307 p->cacheable = p->bufferable = (flags & PAGE_CACHEABLE) != 0; … … 312 326 } 313 327 314 328 NO_TRACE static inline void set_pt_level1_present(pte_t *pt, size_t i) 329 { 330 pte_level1_t *p = &pt[i].l1; 331 332 p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE; 333 } 334 315 335 extern void page_arch_init(void); 316 336 317 318 337 #endif /* __ASM__ */ 319 338 -
kernel/arch/ia32/include/mm/page.h
r7ca22e5 r725d038 115 115 set_pt_flags((pte_t *) (ptl3), (size_t) (i), (x)) 116 116 117 /* Set PTE present bit accessors for each level. */ 118 #define SET_PTL1_PRESENT_ARCH(ptl0, i) \ 119 set_pt_present((pte_t *) (ptl0), (size_t) (i)) 120 #define SET_PTL2_PRESENT_ARCH(ptl1, i) 121 #define SET_PTL3_PRESENT_ARCH(ptl2, i) 122 #define SET_FRAME_PRESENT_ARCH(ptl3, i) \ 123 set_pt_present((pte_t *) (ptl3), (size_t) (i)) 124 117 125 /* Macros for querying the last level entries. */ 118 126 #define PTE_VALID_ARCH(p) \ … … 194 202 } 195 203 204 NO_TRACE static inline void set_pt_present(pte_t *pt, size_t i) 205 { 206 pte_t *p = &pt[i]; 207 208 p->present = 1; 209 } 210 196 211 extern void page_arch_init(void); 197 212 extern void page_fault(unsigned int, istate_t *); -
kernel/arch/ia32/src/mm/page.c
r7ca22e5 r725d038 71 71 for (cur = 0; cur < min(config.identity_size, config.physmem_end); 72 72 cur += FRAME_SIZE) { 73 flags = PAGE_CACHEABLE | PAGE_WRITE; 74 if ((PA2KA(cur) >= config.base) && 75 (PA2KA(cur) < config.base + config.kernel_size)) 76 flags |= PAGE_GLOBAL; 73 flags = PAGE_GLOBAL | PAGE_CACHEABLE | PAGE_WRITE | PAGE_READ; 77 74 page_mapping_insert(AS_KERNEL, PA2KA(cur), cur, flags); 78 75 } -
kernel/arch/ia32/src/smp/apic.c
r7ca22e5 r725d038 259 259 } 260 260 261 #define DELIVS_PENDING_SILENT_RETRIES 4 262 263 static void l_apic_wait_for_delivery(void) 264 { 265 icr_t icr; 266 unsigned retries = 0; 267 268 do { 269 if (retries++ > DELIVS_PENDING_SILENT_RETRIES) { 270 retries = 0; 271 #ifdef CONFIG_DEBUG 272 printf("IPI is pending.\n"); 273 #endif 274 delay(20); 275 } 276 icr.lo = l_apic[ICRlo]; 277 } while (icr.delivs == DELIVS_PENDING); 278 279 } 280 261 281 /** Send all CPUs excluding CPU IPI vector. 262 282 * … … 279 299 280 300 l_apic[ICRlo] = icr.lo; 281 282 icr.lo = l_apic[ICRlo]; 283 if (icr.delivs == DELIVS_PENDING) { 284 #ifdef CONFIG_DEBUG 285 printf("IPI is pending.\n"); 286 #endif 287 } 301 302 l_apic_wait_for_delivery(); 288 303 289 304 return apic_poll_errors(); … … 327 342 return 0; 328 343 344 l_apic_wait_for_delivery(); 345 329 346 icr.lo = l_apic[ICRlo]; 330 if (icr.delivs == DELIVS_PENDING) {331 #ifdef CONFIG_DEBUG332 printf("IPI is pending.\n");333 #endif334 }335 336 347 icr.delmod = DELMOD_INIT; 337 348 icr.destmod = DESTMOD_PHYS; -
kernel/arch/mips32/include/mm/page.h
r7ca22e5 r725d038 128 128 set_pt_flags((pte_t *) (ptl3), (size_t) (i), (x)) 129 129 130 /* Set PTE present bit accessors for each level. */ 131 #define SET_PTL1_PRESENT_ARCH(ptl0, i) \ 132 set_pt_present((pte_t *) (ptl0), (size_t) (i)) 133 #define SET_PTL2_PRESENT_ARCH(ptl1, i) 134 #define SET_PTL3_PRESENT_ARCH(ptl2, i) 135 #define SET_FRAME_PRESENT_ARCH(ptl3, i) \ 136 set_pt_present((pte_t *) (ptl3), (size_t) (i)) 137 130 138 /* Last-level info macros. */ 131 139 #define PTE_VALID_ARCH(pte) (*((uint32_t *) (pte)) != 0) … … 182 190 } 183 191 192 NO_TRACE static inline void set_pt_present(pte_t *pt, size_t i) 193 { 194 pte_t *p = &pt[i]; 195 196 p->p = 1; 197 } 198 199 184 200 extern void page_arch_init(void); 185 201 -
kernel/arch/ppc32/include/mm/page.h
r7ca22e5 r725d038 128 128 #define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \ 129 129 set_pt_flags((pte_t *) (ptl3), (size_t) (i), (x)) 130 131 /* Set PTE present accessors for each level. */ 132 #define SET_PTL1_PRESENT_ARCH(ptl0, i) \ 133 set_pt_present((pte_t *) (ptl0), (size_t) (i)) 134 135 #define SET_PTL2_PRESENT_ARCH(ptl1, i) 136 #define SET_PTL3_PRESENT_ARCH(ptl2, i) 137 138 #define SET_FRAME_PRESENT_ARCH(ptl3, i) \ 139 set_pt_present((pte_t *) (ptl3), (size_t) (i)) 130 140 131 141 /* Macros for querying the last-level PTEs. */ … … 175 185 } 176 186 187 NO_TRACE static inline void set_pt_present(pte_t *pt, size_t i) 188 { 189 pte_t *entry = &pt[i]; 190 191 entry->present = 1; 192 } 193 177 194 extern void page_arch_init(void); 178 195 -
kernel/arch/sparc64/src/smp/sun4u/ipi.c
r7ca22e5 r725d038 124 124 (void) interrupts_disable(); 125 125 } 126 } while ( done);126 } while (!done); 127 127 128 128 preemption_enable(); -
kernel/genarch/include/mm/page_pt.h
r7ca22e5 r725d038 115 115 116 116 /* 117 * These macros are provided to set the present bit within the page tables. 118 * 119 */ 120 #define SET_PTL1_PRESENT(ptl0, i) SET_PTL1_PRESENT_ARCH(ptl0, i) 121 #define SET_PTL2_PRESENT(ptl1, i) SET_PTL2_PRESENT_ARCH(ptl1, i) 122 #define SET_PTL3_PRESENT(ptl2, i) SET_PTL3_PRESENT_ARCH(ptl2, i) 123 #define SET_FRAME_PRESENT(ptl3, i) SET_FRAME_PRESENT_ARCH(ptl3, i) 124 125 /* 117 126 * Macros for querying the last-level PTEs. 118 127 * -
kernel/genarch/src/mm/page_ht.c
r7ca22e5 r725d038 45 45 #include <typedefs.h> 46 46 #include <arch/asm.h> 47 #include <arch/barrier.h> 47 48 #include <synch/spinlock.h> 48 49 #include <arch.h> … … 207 208 pte->page = ALIGN_DOWN(page, PAGE_SIZE); 208 209 pte->frame = ALIGN_DOWN(frame, FRAME_SIZE); 210 211 write_barrier(); 209 212 210 213 hash_table_insert(&page_ht, key, &pte->link); -
kernel/genarch/src/mm/page_pt.c
r7ca22e5 r725d038 43 43 #include <arch/mm/page.h> 44 44 #include <arch/mm/as.h> 45 #include <arch/barrier.h> 45 46 #include <typedefs.h> 46 47 #include <arch/asm.h> … … 86 87 SET_PTL1_ADDRESS(ptl0, PTL0_INDEX(page), KA2PA(newpt)); 87 88 SET_PTL1_FLAGS(ptl0, PTL0_INDEX(page), 88 PAGE_ PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE |89 PAGE_NOT_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE | 89 90 PAGE_WRITE); 91 write_barrier(); 92 SET_PTL1_PRESENT(ptl0, PTL0_INDEX(page)); 90 93 } 91 94 … … 98 101 SET_PTL2_ADDRESS(ptl1, PTL1_INDEX(page), KA2PA(newpt)); 99 102 SET_PTL2_FLAGS(ptl1, PTL1_INDEX(page), 100 PAGE_ PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE |103 PAGE_NOT_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE | 101 104 PAGE_WRITE); 105 write_barrier(); 106 SET_PTL2_PRESENT(ptl1, PTL1_INDEX(page)); 102 107 } 103 108 … … 110 115 SET_PTL3_ADDRESS(ptl2, PTL2_INDEX(page), KA2PA(newpt)); 111 116 SET_PTL3_FLAGS(ptl2, PTL2_INDEX(page), 112 PAGE_ PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE |117 PAGE_NOT_PRESENT | PAGE_USER | PAGE_EXEC | PAGE_CACHEABLE | 113 118 PAGE_WRITE); 119 write_barrier(); 120 SET_PTL3_PRESENT(ptl2, PTL2_INDEX(page)); 114 121 } 115 122 … … 117 124 118 125 SET_FRAME_ADDRESS(ptl3, PTL3_INDEX(page), frame); 119 SET_FRAME_FLAGS(ptl3, PTL3_INDEX(page), flags); 126 SET_FRAME_FLAGS(ptl3, PTL3_INDEX(page), flags | PAGE_NOT_PRESENT); 127 write_barrier(); 128 SET_FRAME_PRESENT(ptl3, PTL3_INDEX(page)); 120 129 } 121 130 … … 279 288 if (GET_PTL1_FLAGS(ptl0, PTL0_INDEX(page)) & PAGE_NOT_PRESENT) 280 289 return NULL; 290 291 read_barrier(); 281 292 282 293 pte_t *ptl1 = (pte_t *) PA2KA(GET_PTL1_ADDRESS(ptl0, PTL0_INDEX(page))); 283 294 if (GET_PTL2_FLAGS(ptl1, PTL1_INDEX(page)) & PAGE_NOT_PRESENT) 284 295 return NULL; 296 297 #if (PTL1_ENTRIES != 0) 298 read_barrier(); 299 #endif 285 300 286 301 pte_t *ptl2 = (pte_t *) PA2KA(GET_PTL2_ADDRESS(ptl1, PTL1_INDEX(page))); 287 302 if (GET_PTL3_FLAGS(ptl2, PTL2_INDEX(page)) & PAGE_NOT_PRESENT) 288 303 return NULL; 304 305 #if (PTL2_ENTRIES != 0) 306 read_barrier(); 307 #endif 289 308 290 309 pte_t *ptl3 = (pte_t *) PA2KA(GET_PTL3_ADDRESS(ptl2, PTL2_INDEX(page))); … … 346 365 SET_PTL1_ADDRESS(ptl0, PTL0_INDEX(addr), KA2PA(l1)); 347 366 SET_PTL1_FLAGS(ptl0, PTL0_INDEX(addr), 348 PAGE_PRESENT | PAGE_USER | PAGE_ EXEC | PAGE_CACHEABLE |349 PAGE_ WRITE);367 PAGE_PRESENT | PAGE_USER | PAGE_CACHEABLE | 368 PAGE_EXEC | PAGE_WRITE | PAGE_READ); 350 369 } 351 370 } -
kernel/generic/src/mm/as.c
r7ca22e5 r725d038 665 665 666 666 page_table_lock(as, false); 667 668 /*669 * Start TLB shootdown sequence.670 */671 ipl_t ipl = tlb_shootdown_start(TLB_INVL_PAGES, as->asid,672 area->base + P2SZ(pages), area->pages - pages);673 667 674 668 /* … … 726 720 } 727 721 722 /* 723 * Start TLB shootdown sequence. 724 * 725 * The sequence is rather short and can be 726 * repeated multiple times. The reason is that 727 * we don't want to have used_space_remove() 728 * inside the sequence as it may use a blocking 729 * memory allocation for its B+tree. Blocking 730 * while holding the tlblock spinlock is 731 * forbidden and would hit a kernel assertion. 732 */ 733 734 ipl_t ipl = tlb_shootdown_start(TLB_INVL_PAGES, 735 as->asid, area->base + P2SZ(pages), 736 area->pages - pages); 737 728 738 for (; i < size; i++) { 729 739 pte_t *pte = page_mapping_find(as, … … 743 753 page_mapping_remove(as, ptr + P2SZ(i)); 744 754 } 755 756 /* 757 * Finish TLB shootdown sequence. 758 */ 759 760 tlb_invalidate_pages(as->asid, 761 area->base + P2SZ(pages), 762 area->pages - pages); 763 764 /* 765 * Invalidate software translation caches 766 * (e.g. TSB on sparc64, PHT on ppc32). 767 */ 768 as_invalidate_translation_cache(as, 769 area->base + P2SZ(pages), 770 area->pages - pages); 771 tlb_shootdown_finalize(ipl); 745 772 } 746 773 } 747 748 /*749 * Finish TLB shootdown sequence.750 */751 752 tlb_invalidate_pages(as->asid, area->base + P2SZ(pages),753 area->pages - pages);754 755 /*756 * Invalidate software translation caches757 * (e.g. TSB on sparc64, PHT on ppc32).758 */759 as_invalidate_translation_cache(as, area->base + P2SZ(pages),760 area->pages - pages);761 tlb_shootdown_finalize(ipl);762 763 774 page_table_unlock(as, false); 764 775 } else { -
kernel/generic/src/mm/tlb.c
r7ca22e5 r725d038 162 162 163 163 size_t i; 164 for (i = 0; i < CPU->tlb_messages_count; CPU->tlb_messages_count--) {164 for (i = 0; i < CPU->tlb_messages_count; i++) { 165 165 tlb_invalidate_type_t type = CPU->tlb_messages[i].type; 166 166 asid_t asid = CPU->tlb_messages[i].asid; … … 188 188 } 189 189 190 CPU->tlb_messages_count = 0; 190 191 irq_spinlock_unlock(&CPU->lock, false); 191 192 CPU->tlb_active = true;
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