Changeset 32573ff in mainline for kernel/arch/amd64/src/amd64.c
- Timestamp:
- 2016-05-02T20:58:16Z (9 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 7c4b26c
- Parents:
- 6adb775f (diff), 5035ba05 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
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kernel/arch/amd64/src/amd64.c
r6adb775f r32573ff 56 56 #include <genarch/multiboot/multiboot.h> 57 57 #include <genarch/multiboot/multiboot2.h> 58 #include <arch/pm.h> 59 #include <arch/vreg.h> 60 #include <arch/kseg.h> 58 61 59 62 #ifdef CONFIG_SMP … … 139 142 void arch_post_mm_init(void) 140 143 { 144 vreg_init(); 145 kseg_init(); 146 141 147 if (config.cpu_active == 1) { 142 148 /* Initialize IRQ routing */ … … 262 268 } 263 269 264 /** Set thread-local-storage pointer265 *266 * TLS pointer is set in FS register. Unfortunately the 64-bit267 * part can be set only in CPL0 mode.268 *269 * The specs say, that on %fs:0 there is stored contents of %fs register,270 * we need not to go to CPL0 to read it.271 */272 sysarg_t sys_tls_set(uintptr_t addr)273 {274 THREAD->arch.tls = addr;275 write_msr(AMD_MSR_FS, addr);276 277 return EOK;278 }279 280 270 /** Construct function pointer 281 271 *
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