Changeset 14f8fd4 in mainline for uspace/drv/bus/usb/ehci/res.c
- Timestamp:
- 2012-03-15T22:52:33Z (13 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- bfb3d60
- Parents:
- 43cd499 (diff), dbbba51c (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the(diff)links above to see all the changes relative to each parent. - File:
-
- 1 moved
-
uspace/drv/bus/usb/ehci/res.c (moved) (moved from uspace/drv/bus/usb/ehci/pci.c ) (7 diffs)
Legend:
- Unmodified
- Added
- Removed
-
uspace/drv/bus/usb/ehci/res.c
r43cd499 r14f8fd4 39 39 #include <str_error.h> 40 40 #include <assert.h> 41 #include <as.h>42 41 #include <devman.h> 43 42 #include <ddi.h> 44 #include <libarch/ddi.h>45 #include <device/hw_res.h>46 47 43 #include <usb/debug.h> 48 #include <pci_dev_iface.h> 49 50 #include "pci.h" 51 52 #define PAGE_SIZE_MASK 0xfffff000 44 #include <device/hw_res_parsed.h> 45 #include <device/pci.h> 46 47 #include "res.h" 53 48 54 49 #define HCC_PARAMS_OFFSET 0x8 … … 72 67 #define WAIT_STEP 10 73 68 74 #define PCI_READ(size) \75 do { \76 async_sess_t *parent_sess = \77 devman_parent_device_connect(EXCHANGE_SERIALIZE, dev->handle, \78 IPC_FLAG_BLOCKING); \79 if (!parent_sess) \80 return ENOMEM; \81 \82 sysarg_t add = (sysarg_t) address; \83 sysarg_t val; \84 \85 async_exch_t *exch = async_exchange_begin(parent_sess); \86 \87 const int ret = \88 async_req_2_1(exch, DEV_IFACE_ID(PCI_DEV_IFACE), \89 IPC_M_CONFIG_SPACE_READ_##size, add, &val); \90 \91 async_exchange_end(exch); \92 async_hangup(parent_sess); \93 \94 assert(value); \95 \96 *value = val; \97 return ret; \98 } while (0)99 100 static int pci_read32(const ddf_dev_t *dev, int address, uint32_t *value)101 {102 PCI_READ(32);103 }104 105 static int pci_read16(const ddf_dev_t *dev, int address, uint16_t *value)106 {107 PCI_READ(16);108 }109 110 static int pci_read8(const ddf_dev_t *dev, int address, uint8_t *value)111 {112 PCI_READ(8);113 }114 115 #define PCI_WRITE(size) \116 do { \117 async_sess_t *parent_sess = \118 devman_parent_device_connect(EXCHANGE_SERIALIZE, dev->handle, \119 IPC_FLAG_BLOCKING); \120 if (!parent_sess) \121 return ENOMEM; \122 \123 sysarg_t add = (sysarg_t) address; \124 sysarg_t val = value; \125 \126 async_exch_t *exch = async_exchange_begin(parent_sess); \127 \128 const int ret = \129 async_req_3_0(exch, DEV_IFACE_ID(PCI_DEV_IFACE), \130 IPC_M_CONFIG_SPACE_WRITE_##size, add, val); \131 \132 async_exchange_end(exch); \133 async_hangup(parent_sess); \134 \135 return ret; \136 } while(0)137 138 static int pci_write32(const ddf_dev_t *dev, int address, uint32_t value)139 {140 PCI_WRITE(32);141 }142 143 static int pci_write16(const ddf_dev_t *dev, int address, uint16_t value)144 {145 PCI_WRITE(16);146 }147 148 static int pci_write8(const ddf_dev_t *dev, int address, uint8_t value)149 {150 PCI_WRITE(8);151 }152 69 153 70 /** Get address of registers and IRQ for given device. … … 159 76 * @return Error code. 160 77 */ 161 int pci_get_my_registers(const ddf_dev_t *dev,78 int get_my_registers(const ddf_dev_t *dev, 162 79 uintptr_t *mem_reg_address, size_t *mem_reg_size, int *irq_no) 163 80 { 164 assert(dev != NULL);81 assert(dev); 165 82 166 async_sess_t *parent_sess = 167 devman_parent_device_connect(EXCHANGE_SERIALIZE, dev->handle, 168 IPC_FLAG_BLOCKING); 83 async_sess_t *parent_sess = devman_parent_device_connect( 84 EXCHANGE_SERIALIZE, dev->handle, IPC_FLAG_BLOCKING); 169 85 if (!parent_sess) 170 86 return ENOMEM; 171 87 172 hw_resource_list_t hw_resources; 173 int rc = hw_res_get_resource_list(parent_sess, &hw_resources); 174 if (rc != EOK) { 175 async_hangup(parent_sess); 176 return rc; 177 } 178 179 uintptr_t mem_address = 0; 180 size_t mem_size = 0; 181 bool mem_found = false; 182 183 int irq = 0; 184 bool irq_found = false; 185 186 size_t i; 187 for (i = 0; i < hw_resources.count; i++) { 188 hw_resource_t *res = &hw_resources.resources[i]; 189 switch (res->type) { 190 case INTERRUPT: 191 irq = res->res.interrupt.irq; 192 irq_found = true; 193 usb_log_debug2("Found interrupt: %d.\n", irq); 194 break; 195 case MEM_RANGE: 196 if (res->res.mem_range.address != 0 197 && res->res.mem_range.size != 0 ) { 198 mem_address = res->res.mem_range.address; 199 mem_size = res->res.mem_range.size; 200 usb_log_debug2("Found mem: %" PRIxn" %zu.\n", 201 mem_address, mem_size); 202 mem_found = true; 203 } 204 default: 205 break; 206 } 207 } 208 209 if (mem_found && irq_found) { 210 *mem_reg_address = mem_address; 211 *mem_reg_size = mem_size; 212 *irq_no = irq; 213 rc = EOK; 214 } else { 215 rc = ENOENT; 216 } 217 88 hw_res_list_parsed_t hw_res; 89 hw_res_list_parsed_init(&hw_res); 90 const int ret = hw_res_get_list_parsed(parent_sess, &hw_res, 0); 218 91 async_hangup(parent_sess); 219 return rc; 92 if (ret != EOK) { 93 return ret; 94 } 95 96 if (hw_res.irqs.count != 1 || hw_res.mem_ranges.count != 1) { 97 hw_res_list_parsed_clean(&hw_res); 98 return ENOENT; 99 } 100 101 if (mem_reg_address) 102 *mem_reg_address = hw_res.mem_ranges.ranges[0].address; 103 if (mem_reg_size) 104 *mem_reg_size = hw_res.mem_ranges.ranges[0].size; 105 if (irq_no) 106 *irq_no = hw_res.irqs.irqs[0]; 107 108 hw_res_list_parsed_clean(&hw_res); 109 return EOK; 220 110 } 221 111 /*----------------------------------------------------------------------------*/ … … 225 115 * @return Error code. 226 116 */ 227 int pci_enable_interrupts(const ddf_dev_t *device)117 int enable_interrupts(const ddf_dev_t *device) 228 118 { 229 async_sess_t *parent_sess = 230 devman_parent_device_connect(EXCHANGE_SERIALIZE, device->handle, 231 IPC_FLAG_BLOCKING); 119 async_sess_t *parent_sess = devman_parent_device_connect( 120 EXCHANGE_SERIALIZE, device->handle, IPC_FLAG_BLOCKING); 232 121 if (!parent_sess) 233 122 return ENOMEM; … … 239 128 } 240 129 /*----------------------------------------------------------------------------*/ 241 /** Implements BIOS handoff routine as decribed in EHCI spec 242 * 243 * @param[in] device Device asking for interrupts 130 /** Implements BIOS hands-off routine as described in EHCI spec 131 * 132 * @param device EHCI device 133 * @param eecp Value of EHCI Extended Capabilities pointer. 244 134 * @return Error code. 245 135 */ 246 int pci_disable_legacy( 247 const ddf_dev_t *device, uintptr_t reg_base, size_t reg_size, int irq) 136 static int disable_extended_caps(const ddf_dev_t *device, unsigned eecp) 137 { 138 /* nothing to do */ 139 if (eecp == 0) 140 return EOK; 141 142 async_sess_t *parent_sess = devman_parent_device_connect( 143 EXCHANGE_SERIALIZE, device->handle, IPC_FLAG_BLOCKING); 144 if (!parent_sess) 145 return ENOMEM; 146 147 #define CHECK_RET_HANGUP_RETURN(ret, message...) \ 148 if (ret != EOK) { \ 149 usb_log_error(message); \ 150 async_hangup(parent_sess); \ 151 return ret; \ 152 } else (void)0 153 154 /* Read the first EEC. i.e. Legacy Support register */ 155 uint32_t usblegsup; 156 int ret = pci_config_space_read_32(parent_sess, 157 eecp + USBLEGSUP_OFFSET, &usblegsup); 158 CHECK_RET_HANGUP_RETURN(ret, 159 "Failed to read USBLEGSUP: %s.\n", str_error(ret)); 160 usb_log_debug("USBLEGSUP: %" PRIx32 ".\n", usblegsup); 161 162 /* Request control from firmware/BIOS by writing 1 to highest 163 * byte. (OS Control semaphore)*/ 164 usb_log_debug("Requesting OS control.\n"); 165 ret = pci_config_space_write_8(parent_sess, 166 eecp + USBLEGSUP_OFFSET + 3, 1); 167 CHECK_RET_HANGUP_RETURN(ret, "Failed to request OS EHCI control: %s.\n", 168 str_error(ret)); 169 170 size_t wait = 0; 171 /* Wait for BIOS to release control. */ 172 ret = pci_config_space_read_32( 173 parent_sess, eecp + USBLEGSUP_OFFSET, &usblegsup); 174 while ((wait < DEFAULT_WAIT) && (usblegsup & USBLEGSUP_BIOS_CONTROL)) { 175 async_usleep(WAIT_STEP); 176 ret = pci_config_space_read_32(parent_sess, 177 eecp + USBLEGSUP_OFFSET, &usblegsup); 178 wait += WAIT_STEP; 179 } 180 181 if ((usblegsup & USBLEGSUP_BIOS_CONTROL) == 0) { 182 usb_log_info("BIOS released control after %zu usec.\n", wait); 183 async_hangup(parent_sess); 184 return EOK; 185 } 186 187 /* BIOS failed to hand over control, this should not happen. */ 188 usb_log_warning( "BIOS failed to release control after " 189 "%zu usecs, force it.\n", wait); 190 ret = pci_config_space_write_32(parent_sess, 191 eecp + USBLEGSUP_OFFSET, USBLEGSUP_OS_CONTROL); 192 CHECK_RET_HANGUP_RETURN(ret, "Failed to force OS control: " 193 "%s.\n", str_error(ret)); 194 /* 195 * Check capability type here, value of 01h identifies the capability 196 * as Legacy Support. This extended capability requires one additional 197 * 32-bit register for control/status information and this register is 198 * located at offset EECP+04h 199 */ 200 if ((usblegsup & 0xff) == 1) { 201 /* Read the second EEC Legacy Support and Control register */ 202 uint32_t usblegctlsts; 203 ret = pci_config_space_read_32(parent_sess, 204 eecp + USBLEGCTLSTS_OFFSET, &usblegctlsts); 205 CHECK_RET_HANGUP_RETURN(ret, "Failed to get USBLEGCTLSTS: %s.\n", 206 str_error(ret)); 207 usb_log_debug("USBLEGCTLSTS: %" PRIx32 ".\n", usblegctlsts); 208 /* 209 * Zero SMI enables in legacy control register. 210 * It should prevent pre-OS code from 211 * interfering. NOTE: Three upper bits are WC 212 */ 213 ret = pci_config_space_write_32(parent_sess, 214 eecp + USBLEGCTLSTS_OFFSET, 0xe0000000); 215 CHECK_RET_HANGUP_RETURN(ret, "Failed(%d) zero USBLEGCTLSTS.\n", ret); 216 udelay(10); 217 ret = pci_config_space_read_32(parent_sess, 218 eecp + USBLEGCTLSTS_OFFSET, &usblegctlsts); 219 CHECK_RET_HANGUP_RETURN(ret, "Failed to get USBLEGCTLSTS 2: %s.\n", 220 str_error(ret)); 221 usb_log_debug("Zeroed USBLEGCTLSTS: %" PRIx32 ".\n", 222 usblegctlsts); 223 } 224 225 /* Read again Legacy Support register */ 226 ret = pci_config_space_read_32(parent_sess, 227 eecp + USBLEGSUP_OFFSET, &usblegsup); 228 CHECK_RET_HANGUP_RETURN(ret, "Failed to read USBLEGSUP: %s.\n", 229 str_error(ret)); 230 usb_log_debug("USBLEGSUP: %" PRIx32 ".\n", usblegsup); 231 async_hangup(parent_sess); 232 return EOK; 233 #undef CHECK_RET_HANGUP_RETURN 234 } 235 236 int disable_legacy(const ddf_dev_t *device, uintptr_t reg_base, size_t reg_size) 248 237 { 249 238 assert(device); 250 (void) pci_read16;251 (void) pci_read8;252 (void) pci_write16;253 239 254 240 #define CHECK_RET_RETURN(ret, message...) \ … … 274 260 usb_log_debug("Value of EECP: %x.\n", eecp); 275 261 276 /* Read the first EEC. i.e. Legacy Support register */ 277 uint32_t usblegsup; 278 ret = pci_read32(device, eecp + USBLEGSUP_OFFSET, &usblegsup); 279 CHECK_RET_RETURN(ret, "Failed to read USBLEGSUP: %s.\n", str_error(ret)); 280 usb_log_debug("USBLEGSUP: %" PRIx32 ".\n", usblegsup); 281 282 /* Request control from firmware/BIOS, by writing 1 to highest byte. 283 * (OS Control semaphore)*/ 284 usb_log_debug("Requesting OS control.\n"); 285 ret = pci_write8(device, eecp + USBLEGSUP_OFFSET + 3, 1); 286 CHECK_RET_RETURN(ret, "Failed to request OS EHCI control: %s.\n", 262 ret = disable_extended_caps(device, eecp); 263 CHECK_RET_RETURN(ret, "Failed to disable extended capabilities: %s.\n", 287 264 str_error(ret)); 288 265 289 size_t wait = 0; 290 /* Wait for BIOS to release control. */ 291 ret = pci_read32(device, eecp + USBLEGSUP_OFFSET, &usblegsup); 292 while ((wait < DEFAULT_WAIT) && (usblegsup & USBLEGSUP_BIOS_CONTROL)) { 293 async_usleep(WAIT_STEP); 294 ret = pci_read32(device, eecp + USBLEGSUP_OFFSET, &usblegsup); 295 wait += WAIT_STEP; 296 } 297 298 299 if ((usblegsup & USBLEGSUP_BIOS_CONTROL) == 0) { 300 usb_log_info("BIOS released control after %zu usec.\n", wait); 301 } else { 302 /* BIOS failed to hand over control, this should not happen. */ 303 usb_log_warning( "BIOS failed to release control after " 304 "%zu usecs, force it.\n", wait); 305 ret = pci_write32(device, eecp + USBLEGSUP_OFFSET, 306 USBLEGSUP_OS_CONTROL); 307 CHECK_RET_RETURN(ret, "Failed to force OS control: %s.\n", 308 str_error(ret)); 309 /* Check capability type here, A value of 01h 310 * identifies the capability as Legacy Support. 311 * This extended capability requires one 312 * additional 32-bit register for control/status information, 313 * and this register is located at offset EECP+04h 314 * */ 315 if ((usblegsup & 0xff) == 1) { 316 /* Read the second EEC 317 * Legacy Support and Control register */ 318 uint32_t usblegctlsts; 319 ret = pci_read32( 320 device, eecp + USBLEGCTLSTS_OFFSET, &usblegctlsts); 321 CHECK_RET_RETURN(ret, 322 "Failed to get USBLEGCTLSTS: %s.\n", str_error(ret)); 323 usb_log_debug("USBLEGCTLSTS: %" PRIx32 ".\n", 324 usblegctlsts); 325 /* Zero SMI enables in legacy control register. 326 * It should prevent pre-OS code from interfering. */ 327 ret = pci_write32(device, eecp + USBLEGCTLSTS_OFFSET, 328 0xe0000000); /* three upper bits are WC */ 329 CHECK_RET_RETURN(ret, 330 "Failed(%d) zero USBLEGCTLSTS.\n", ret); 331 udelay(10); 332 ret = pci_read32( 333 device, eecp + USBLEGCTLSTS_OFFSET, &usblegctlsts); 334 CHECK_RET_RETURN(ret, 335 "Failed to get USBLEGCTLSTS 2: %s.\n", 336 str_error(ret)); 337 usb_log_debug("Zeroed USBLEGCTLSTS: %" PRIx32 ".\n", 338 usblegctlsts); 339 } 340 } 341 342 343 /* Read again Legacy Support register */ 344 ret = pci_read32(device, eecp + USBLEGSUP_OFFSET, &usblegsup); 345 CHECK_RET_RETURN(ret, "Failed to read USBLEGSUP: %s.\n", str_error(ret)); 346 usb_log_debug("USBLEGSUP: %" PRIx32 ".\n", usblegsup); 266 #undef CHECK_RET_RETURN 347 267 348 268 /* 349 * TURN OFF EHCI FOR NOW, DRIVER WILL REINITIALIZE IT 269 * TURN OFF EHCI FOR NOW, DRIVER WILL REINITIALIZE IT IF NEEDED 350 270 */ 351 271 … … 384 304 385 305 return ret; 386 #undef CHECK_RET_RETURN387 306 } 388 307
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