sparc64
[Memory management]


Files

file  as.h
file  asid.h
file  frame.h
file  memory_init.h
file  mmu.h
file  page.h
file  tlb.h
file  tte.h
file  as.c
file  frame.c
file  memory_init.c
file  page.c
file  tlb.c

Data Structures

union  lsu_cr_reg
union  tlb_context_reg
union  tlb_data_access_addr
union  tlb_tag_read_reg
union  tlb_demap_addr
union  tlb_sfsr_reg
union  tte_tag
union  tte_data

Defines

#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH   1
#define KERNEL_ADDRESS_SPACE_START_ARCH   (unsigned long) 0x0000000000000000
#define KERNEL_ADDRESS_SPACE_END_ARCH   (unsigned long) 0xffffffffffffffff
#define USER_ADDRESS_SPACE_START_ARCH   (unsigned long) 0x0000000000000000
#define USER_ADDRESS_SPACE_END_ARCH   (unsigned long) 0xffffffffffffffff
#define USTACK_ADDRESS_ARCH   (0x7fffffffffffffff-(PAGE_SIZE-1))
#define as_install_arch(as)
#define ASID_MAX_ARCH   8191
#define FRAME_WIDTH   13
#define FRAME_SIZE   (1<<FRAME_WIDTH)
#define ASI_LSU_CONTROL_REG   0x45
#define ASI_IMMU   0x50
#define ASI_IMMU_TSB_8KB_PTR_REG   0x51
#define ASI_IMMU_TSB_64KB_PTR_REG   0x52
#define ASI_ITLB_DATA_IN_REG   0x54
#define ASI_ITLB_DATA_ACCESS_REG   0x55
#define ASI_ITLB_TAG_READ_REG   0x56
#define ASI_IMMU_DEMAP   0x57
#define VA_IMMU_TAG_TARGET   0x0
#define VA_IMMU_SFSR   0x18
#define VA_IMMU_TSB_BASE   0x28
#define VA_IMMU_TAG_ACCESS   0x30
#define ASI_DMMU   0x58
#define ASI_DMMU_TSB_8KB_PTR_REG   0x59
#define ASI_DMMU_TSB_64KB_PTR_REG   0x5a
#define ASI_DMMU_TSB_DIRECT_PTR_REG   0x5b
#define ASI_DTLB_DATA_IN_REG   0x5c
#define ASI_DTLB_DATA_ACCESS_REG   0x5d
#define ASI_DTLB_TAG_READ_REG   0x5e
#define ASI_DMMU_DEMAP   0x5f
#define VA_DMMU_TAG_TARGET   0x0
#define VA_PRIMARY_CONTEXT_REG   0x8
#define VA_SECONDARY_CONTEXT_REG   0x10
#define VA_DMMU_SFSR   0x18
#define VA_DMMU_SFAR   0x20
#define VA_DMMU_TSB_BASE   0x28
#define VA_DMMU_TAG_ACCESS   0x30
#define VA_DMMU_VA_WATCHPOINT_REG   0x38
#define VA_DMMU_PA_WATCHPOINT_REG   0x40
#define immu_enable()   immu_set(true)
#define immu_disable()   immu_set(false)
#define dmmu_enable()   dmmu_set(true)
#define dmmu_disable()   dmmu_set(false)
#define PAGE_WIDTH   FRAME_WIDTH
#define PAGE_SIZE   FRAME_SIZE
#define ITLB_ENTRY_COUNT   64
#define DTLB_ENTRY_COUNT   64
#define PAGESIZE_8K   0
#define PAGESIZE_64K   1
#define PAGESIZE_512K   2
#define PAGESIZE_4M   3
#define KERNEL_PAGE_WIDTH   22
#define TLB_DEMAP_PAGE   0
#define TLB_DEMAP_CONTEXT   1
#define TLB_DEMAP_PRIMARY   0
#define TLB_DEMAP_SECONDARY   1
#define TLB_DEMAP_NUCLEUS   2

Typedefs

typedef __u16 asid_t
typedef lsu_cr_reg lsu_cr_reg_t
typedef tlb_context_reg tlb_context_reg_t
typedef tte_data_t tlb_data_t
typedef tlb_data_access_addr tlb_data_access_addr_t
typedef tlb_data_access_addr tlb_tag_read_addr_t
typedef tlb_tag_read_reg tlb_tag_read_reg_t
typedef tlb_tag_read_reg tlb_tag_access_reg_t
typedef tlb_demap_addr tlb_demap_addr_t
typedef tlb_sfsr_reg tlb_sfsr_reg_t
typedef tte_tag tte_tag_t
typedef tte_data tte_data_t

Functions

void as_arch_init (void)
size_t get_memory_size (void)
static void immu_set (bool enable)
static void dmmu_set (bool enable)
static __u64 mmu_primary_context_read (void)
static void mmu_primary_context_write (__u64 v)
static __u64 mmu_secondary_context_read (void)
static void mmu_secondary_context_write (__u64 v)
static __u64 itlb_data_access_read (index_t entry)
static void itlb_data_access_write (index_t entry, __u64 value)
static __u64 dtlb_data_access_read (index_t entry)
static void dtlb_data_access_write (index_t entry, __u64 value)
static __u64 itlb_tag_read_read (index_t entry)
static __u64 dtlb_tag_read_read (index_t entry)
static void itlb_tag_access_write (__u64 v)
static __u64 itlb_tag_access_read (void)
static void dtlb_tag_access_write (__u64 v)
static __u64 dtlb_tag_access_read (void)
static void itlb_data_in_write (__u64 v)
static void dtlb_data_in_write (__u64 v)
static __u64 itlb_sfsr_read (void)
static void itlb_sfsr_write (__u64 v)
static __u64 dtlb_sfsr_read (void)
static void dtlb_sfsr_write (__u64 v)
static __u64 dtlb_sfar_read (void)
static void itlb_demap (int type, int context_encoding, __address page)
static void dtlb_demap (int type, int context_encoding, __address page)
void fast_instruction_access_mmu_miss (void)
void fast_data_access_mmu_miss (void)
void fast_data_access_protection (void)
void dtlb_insert_mapping (__address page, __address frame, int pagesize, bool locked, bool cacheable)
void frame_arch_init (void)
void page_arch_init (void)
__address hw_map (__address physaddr, size_t size)
void tlb_arch_init (void)
void tlb_print (void)
void tlb_invalidate_all (void)
void tlb_invalidate_asid (asid_t asid)
void tlb_invalidate_pages (asid_t asid, __address page, count_t cnt)

Variables

char * context_encoding []

Define Documentation

#define as_install_arch (  as   ) 
 

Definition at line 47 of file as.h.

Referenced by as_switch().

#define ASI_DMMU   0x58
 

D-MMU ASIs.

Definition at line 62 of file mmu.h.

Referenced by dtlb_sfar_read(), dtlb_sfsr_read(), dtlb_sfsr_write(), dtlb_tag_access_read(), dtlb_tag_access_write(), mmu_primary_context_read(), mmu_primary_context_write(), mmu_secondary_context_read(), and mmu_secondary_context_write().

#define ASI_DMMU_DEMAP   0x5f
 

Definition at line 69 of file mmu.h.

Referenced by dtlb_demap().

#define ASI_DMMU_TSB_64KB_PTR_REG   0x5a
 

Definition at line 64 of file mmu.h.

#define ASI_DMMU_TSB_8KB_PTR_REG   0x59
 

Definition at line 63 of file mmu.h.

#define ASI_DMMU_TSB_DIRECT_PTR_REG   0x5b
 

Definition at line 65 of file mmu.h.

#define ASI_DTLB_DATA_ACCESS_REG   0x5d
 

Definition at line 67 of file mmu.h.

Referenced by dtlb_data_access_read(), and dtlb_data_access_write().

#define ASI_DTLB_DATA_IN_REG   0x5c
 

Definition at line 66 of file mmu.h.

Referenced by dtlb_data_in_write().

#define ASI_DTLB_TAG_READ_REG   0x5e
 

Definition at line 68 of file mmu.h.

Referenced by dtlb_tag_read_read().

#define ASI_IMMU   0x50
 

I-MMU ASIs.

Definition at line 47 of file mmu.h.

Referenced by itlb_sfsr_read(), itlb_sfsr_write(), itlb_tag_access_read(), and itlb_tag_access_write().

#define ASI_IMMU_DEMAP   0x57
 

Definition at line 53 of file mmu.h.

Referenced by itlb_demap().

#define ASI_IMMU_TSB_64KB_PTR_REG   0x52
 

Definition at line 49 of file mmu.h.

#define ASI_IMMU_TSB_8KB_PTR_REG   0x51
 

Definition at line 48 of file mmu.h.

#define ASI_ITLB_DATA_ACCESS_REG   0x55
 

Definition at line 51 of file mmu.h.

Referenced by itlb_data_access_read(), and itlb_data_access_write().

#define ASI_ITLB_DATA_IN_REG   0x54
 

Definition at line 50 of file mmu.h.

Referenced by itlb_data_in_write().

#define ASI_ITLB_TAG_READ_REG   0x56
 

Definition at line 52 of file mmu.h.

Referenced by itlb_tag_read_read().

#define ASI_LSU_CONTROL_REG   0x45
 

LSU Control Register ASI. Load/Store Unit Control Register.

Definition at line 44 of file mmu.h.

Referenced by dmmu_set(), and immu_set().

#define ASID_MAX_ARCH   8191
 

Definition at line 45 of file asid.h.

 
#define dmmu_disable (   )     dmmu_set(false)
 

Definition at line 109 of file mmu.h.

Referenced by tlb_arch_init().

 
#define dmmu_enable (   )     dmmu_set(true)
 

Definition at line 108 of file mmu.h.

Referenced by tlb_arch_init().

#define DTLB_ENTRY_COUNT   64
 

Definition at line 47 of file tlb.h.

#define FRAME_SIZE   (1<<FRAME_WIDTH)
 

Definition at line 39 of file frame.h.

Referenced by anon_page_fault(), elf_frame_free(), elf_page_fault(), fast_data_access_mmu_miss(), ht_mapping_insert(), hw_map(), phys_page_fault(), and sys_physmem_map().

#define FRAME_WIDTH   13
 

Definition at line 38 of file frame.h.

Referenced by ADDR2PFN(), hw_map(), PFN2ADDR(), and SIZE2FRAMES().

 
#define immu_disable (   )     immu_set(false)
 

Definition at line 107 of file mmu.h.

Referenced by tlb_arch_init().

 
#define immu_enable (   )     immu_set(true)
 

Definition at line 106 of file mmu.h.

Referenced by tlb_arch_init().

#define ITLB_ENTRY_COUNT   64
 

Definition at line 46 of file tlb.h.

Referenced by tlb_invalidate_all(), and tlb_print().

#define KERNEL_ADDRESS_SPACE_END_ARCH   (unsigned long) 0xffffffffffffffff
 

Definition at line 41 of file as.h.

#define KERNEL_ADDRESS_SPACE_SHADOWED_ARCH   1
 

Definition at line 38 of file as.h.

#define KERNEL_ADDRESS_SPACE_START_ARCH   (unsigned long) 0x0000000000000000
 

Definition at line 40 of file as.h.

#define KERNEL_PAGE_WIDTH   22
 

Bit width of the TLB-locked portion of kernel address space.

Definition at line 56 of file tlb.h.

Referenced by after_thread_ran_arch(), and before_thread_runs_arch().

#define PAGE_SIZE   FRAME_SIZE
 

Definition at line 41 of file page.h.

Referenced by anon_page_fault(), anon_share(), as_area_create(), as_area_destroy(), as_area_resize(), as_area_share(), as_get_size(), badness(), check_area_conflicts(), comp_objects(), ddi_physmem_map(), elf_frame_free(), elf_page_fault(), elf_share(), fast_data_access_mmu_miss(), find_area_and_lock(), ht_mapping_find(), ht_mapping_insert(), ht_mapping_remove(), hw_map(), klog_init(), load_segment(), main_bsp(), map_structure(), ofw_init_zones(), phys_page_fault(), slab_space_alloc(), sys_futex_sleep_timeout(), sys_futex_wakeup(), sys_io(), sys_physmem_map(), task_run_program(), tlb_invalidate_pages(), used_space_insert(), and used_space_remove().

#define PAGE_WIDTH   FRAME_WIDTH
 

Definition at line 40 of file page.h.

Referenced by as_area_resize(), elf_frame_free(), elf_page_fault(), and hash().

#define PAGESIZE_4M   3
 

Definition at line 53 of file tlb.h.

Referenced by hw_map(), and tlb_arch_init().

#define PAGESIZE_512K   2
 

Definition at line 52 of file tlb.h.

Referenced by hw_map().

#define PAGESIZE_64K   1
 

Definition at line 51 of file tlb.h.

Referenced by hw_map().

#define PAGESIZE_8K   0
 

Page sizes.

Definition at line 50 of file tlb.h.

Referenced by before_thread_runs_arch(), fast_data_access_mmu_miss(), and hw_map().

#define TLB_DEMAP_CONTEXT   1
 

Definition at line 95 of file tlb.h.

Referenced by tlb_arch_init(), and tlb_invalidate_asid().

#define TLB_DEMAP_NUCLEUS   2
 

Definition at line 100 of file tlb.h.

Referenced by after_thread_ran_arch(), before_thread_runs_arch(), tlb_arch_init(), tlb_invalidate_asid(), and tlb_invalidate_pages().

#define TLB_DEMAP_PAGE   0
 

TLB Demap Operation types.

Definition at line 94 of file tlb.h.

Referenced by after_thread_ran_arch(), before_thread_runs_arch(), and tlb_invalidate_pages().

#define TLB_DEMAP_PRIMARY   0
 

TLB Demap Operation Context register encodings.

Definition at line 98 of file tlb.h.

#define TLB_DEMAP_SECONDARY   1
 

Definition at line 99 of file tlb.h.

#define USER_ADDRESS_SPACE_END_ARCH   (unsigned long) 0xffffffffffffffff
 

Definition at line 43 of file as.h.

#define USER_ADDRESS_SPACE_START_ARCH   (unsigned long) 0x0000000000000000
 

Definition at line 42 of file as.h.

#define USTACK_ADDRESS_ARCH   (0x7fffffffffffffff-(PAGE_SIZE-1))
 

Definition at line 45 of file as.h.

#define VA_DMMU_PA_WATCHPOINT_REG   0x40
 

DMMU PA data watchpoint register.

Definition at line 80 of file mmu.h.

#define VA_DMMU_SFAR   0x20
 

DMMU sync fault address register.

Definition at line 76 of file mmu.h.

Referenced by dtlb_sfar_read().

#define VA_DMMU_SFSR   0x18
 

DMMU sync fault status register.

Definition at line 75 of file mmu.h.

Referenced by dtlb_sfsr_read(), and dtlb_sfsr_write().

#define VA_DMMU_TAG_ACCESS   0x30
 

DMMU TLB tag access register.

Definition at line 78 of file mmu.h.

Referenced by dtlb_tag_access_read(), and dtlb_tag_access_write().

#define VA_DMMU_TAG_TARGET   0x0
 

Virtual Addresses within ASI_DMMU. DMMU tag target register.

Definition at line 72 of file mmu.h.

#define VA_DMMU_TSB_BASE   0x28
 

DMMU TSB base register.

Definition at line 77 of file mmu.h.

#define VA_DMMU_VA_WATCHPOINT_REG   0x38
 

DMMU VA data watchpoint register.

Definition at line 79 of file mmu.h.

#define VA_IMMU_SFSR   0x18
 

IMMU sync fault status register.

Definition at line 57 of file mmu.h.

Referenced by itlb_sfsr_read(), and itlb_sfsr_write().

#define VA_IMMU_TAG_ACCESS   0x30
 

IMMU TLB tag access register.

Definition at line 59 of file mmu.h.

Referenced by itlb_tag_access_read(), and itlb_tag_access_write().

#define VA_IMMU_TAG_TARGET   0x0
 

Virtual Addresses within ASI_IMMU. IMMU tag target register.

Definition at line 56 of file mmu.h.

#define VA_IMMU_TSB_BASE   0x28
 

IMMU TSB base register.

Definition at line 58 of file mmu.h.

#define VA_PRIMARY_CONTEXT_REG   0x8
 

DMMU primary context register.

Definition at line 73 of file mmu.h.

Referenced by mmu_primary_context_read(), mmu_primary_context_write(), and mmu_secondary_context_write().

#define VA_SECONDARY_CONTEXT_REG   0x10
 

DMMU secondary context register.

Definition at line 74 of file mmu.h.

Referenced by mmu_secondary_context_read().

Typedef Documentation

typedef __u16 asid_t
 

Definition at line 43 of file asid.h.

typedef union lsu_cr_reg lsu_cr_reg_t
 

Definition at line 103 of file mmu.h.

typedef union tlb_context_reg tlb_context_reg_t
 

Definition at line 65 of file tlb.h.

typedef union tlb_data_access_addr tlb_data_access_addr_t
 

Definition at line 79 of file tlb.h.

typedef tte_data_t tlb_data_t
 

I-/D-TLB Data In/Access Register type.

Definition at line 68 of file tlb.h.

typedef union tlb_demap_addr tlb_demap_addr_t
 

Definition at line 113 of file tlb.h.

typedef union tlb_sfsr_reg tlb_sfsr_reg_t
 

Definition at line 133 of file tlb.h.

typedef union tlb_tag_read_reg tlb_tag_access_reg_t
 

Definition at line 91 of file tlb.h.

typedef union tlb_data_access_addr tlb_tag_read_addr_t
 

Definition at line 80 of file tlb.h.

typedef union tlb_tag_read_reg tlb_tag_read_reg_t
 

Definition at line 90 of file tlb.h.

typedef union tte_data tte_data_t
 

Definition at line 76 of file tte.h.

typedef union tte_tag tte_tag_t
 

Definition at line 52 of file tte.h.

Function Documentation

void as_arch_init (  void   ) 
 

Architecture dependent address space init.

Definition at line 40 of file as.c.

References as_ht_operations, as_operations, and asid_fifo_init().

Referenced by as_init().

Here is the call graph for this function:

static void dmmu_set (  bool  enable  )  [static]
 

Disable or Enable DMMU.

Definition at line 123 of file mmu.h.

References ASI_LSU_CONTROL_REG, asi_u64_read(), asi_u64_write(), lsu_cr_reg::dm, membar(), and lsu_cr_reg::value.

Here is the call graph for this function:

static __u64 dtlb_data_access_read (  index_t  entry  )  [static]
 

Read DMMU TLB Data Access Register.

Parameters:
entry TLB Entry index.
Returns:
Current value of specified DMMU TLB Data Access Register.

Definition at line 209 of file tlb.h.

References ASI_DTLB_DATA_ACCESS_REG, asi_u64_read(), tlb_data_access_addr::tlb_entry, and tlb_data_access_addr::value.

Here is the call graph for this function:

static void dtlb_data_access_write (  index_t  entry,
__u64  value
)  [static]
 

Write DMMU TLB Data Access Register.

Parameters:
entry TLB Entry index.
value Value to be written.

Definition at line 223 of file tlb.h.

References ASI_DTLB_DATA_ACCESS_REG, asi_u64_write(), flush(), tlb_data_access_addr::tlb_entry, and tlb_data_access_addr::value.

Here is the call graph for this function:

static void dtlb_data_in_write (  __u64  v  )  [static]
 

Write DMMU TLB Data in Register.

Parameters:
v Value to be written.

Definition at line 316 of file tlb.h.

References ASI_DTLB_DATA_IN_REG, asi_u64_write(), and flush().

Referenced by dtlb_insert_mapping(), and tlb_arch_init().

Here is the call graph for this function:

static void dtlb_demap (  int  type,
int  context_encoding,
__address  page
)  [static]
 

Perform DMMU TLB Demap Operation.

Parameters:
type Selects between context and page demap.
context_encoding Specifies which Context register has Context ID for demap.
page Address which is on the page to be demapped.

Definition at line 397 of file tlb.h.

References ASI_DMMU_DEMAP, asi_u64_write(), tlb_demap_addr::context, flush(), tlb_demap_addr::type, tlb_demap_addr::value, and tlb_demap_addr::vpn.

Referenced by after_thread_ran_arch(), before_thread_runs_arch(), tlb_arch_init(), tlb_invalidate_asid(), and tlb_invalidate_pages().

Here is the call graph for this function:

void dtlb_insert_mapping (  __address  page,
__address  frame,
int  pagesize,
bool  locked,
bool  cacheable
) 
 

Insert privileged mapping into DMMU TLB.

Parameters:
page Virtual page address.
frame Physical frame address.
pagesize Page size.
locked True for permanent mappings, false otherwise.
cacheable True if the mapping is cacheable, false otherwise.

Definition at line 134 of file tlb.c.

References ASID_KERNEL, tte_data::cp, tte_data::cv, dtlb_data_in_write(), dtlb_tag_access_write(), tte_data::g, tte_data::l, tte_data::p, tte_data::pfn, tte_data::size, tte_data::v, tte_data::value, tlb_tag_read_reg::value, tlb_tag_read_reg::vpn, and tte_data::w.

Referenced by before_thread_runs_arch(), fast_data_access_mmu_miss(), and hw_map().

Here is the call graph for this function:

static __u64 dtlb_sfar_read (  void   )  [static]
 

Read DTLB Synchronous Fault Address Register.

Returns:
Current content of D-SFAR register.

Definition at line 364 of file tlb.h.

References ASI_DMMU, asi_u64_read(), and VA_DMMU_SFAR.

Here is the call graph for this function:

static __u64 dtlb_sfsr_read (  void   )  [static]
 

Read DTLB Synchronous Fault Status Register.

Returns:
Current content of D-SFSR register.

Definition at line 345 of file tlb.h.

References ASI_DMMU, asi_u64_read(), and VA_DMMU_SFSR.

Here is the call graph for this function:

static void dtlb_sfsr_write (  __u64  v  )  [static]
 

Write DTLB Synchronous Fault Status Register.

Parameters:
v New value of D-SFSR register.

Definition at line 354 of file tlb.h.

References ASI_DMMU, asi_u64_write(), flush(), and VA_DMMU_SFSR.

Here is the call graph for this function:

static __u64 dtlb_tag_access_read (  void   )  [static]
 

Read DMMU TLB Tag Access Register.

Returns:
Current value of DMMU TLB Tag Access Register.

Definition at line 296 of file tlb.h.

References ASI_DMMU, asi_u64_read(), and VA_DMMU_TAG_ACCESS.

Referenced by fast_data_access_mmu_miss().

Here is the call graph for this function:

static void dtlb_tag_access_write (  __u64  v  )  [static]
 

Write DMMU TLB Tag Access Register.

Parameters:
v Value to be written.

Definition at line 286 of file tlb.h.

References ASI_DMMU, asi_u64_write(), flush(), and VA_DMMU_TAG_ACCESS.

Referenced by dtlb_insert_mapping(), and tlb_arch_init().

Here is the call graph for this function:

static __u64 dtlb_tag_read_read (  index_t  entry  )  [static]
 

Read DMMU TLB Tag Read Register.

Parameters:
entry TLB Entry index.
Returns:
Current value of specified DMMU TLB Tag Read Register.

Definition at line 254 of file tlb.h.

References ASI_DTLB_TAG_READ_REG, asi_u64_read(), tlb_data_access_addr::tlb_entry, and tlb_data_access_addr::value.

Here is the call graph for this function:

void fast_data_access_mmu_miss (  void   ) 
 

DTLB miss handler.

Definition at line 170 of file tlb.c.

References ASID_KERNEL, tlb_tag_read_reg::context, dtlb_insert_mapping(), dtlb_tag_access_read(), FRAME_SIZE, get_symtab_entry(), PAGE_SIZE, PAGESIZE_8K, panic, printf(), tpc_read(), tlb_tag_read_reg::value, and tlb_tag_read_reg::vpn.

Here is the call graph for this function:

void fast_data_access_protection (  void   ) 
 

DTLB protection fault handler.

Definition at line 193 of file tlb.c.

References panic.

void fast_instruction_access_mmu_miss (  void   ) 
 

ITLB miss handler.

Definition at line 164 of file tlb.c.

References panic.

void frame_arch_init (  void   ) 
 

Definition at line 41 of file frame.c.

References frame_mark_unavailable(), and ofw_init_zones().

Referenced by frame_init().

Here is the call graph for this function:

size_t get_memory_size (  void   ) 
 

Definition at line 39 of file memory_init.c.

References ofw_get_memory_size().

Referenced by main_bsp().

Here is the call graph for this function:

__address hw_map (  __address  physaddr,
size_t  size
) 
 

Definition at line 47 of file page.c.

References ASSERT, count, dtlb_insert_mapping(), fnzb32(), frame_alloc, FRAME_KA, FRAME_SIZE, FRAME_WIDTH, PAGE_SIZE, PAGESIZE_4M, PAGESIZE_512K, PAGESIZE_64K, PAGESIZE_8K, and PFN2ADDR().

Referenced by fb_init(), and kbd_init().

Here is the call graph for this function:

static void immu_set (  bool  enable  )  [static]
 

Disable or Enable IMMU.

Definition at line 112 of file mmu.h.

References ASI_LSU_CONTROL_REG, asi_u64_read(), asi_u64_write(), lsu_cr_reg::im, membar(), and lsu_cr_reg::value.

Here is the call graph for this function:

static __u64 itlb_data_access_read (  index_t  entry  )  [static]
 

Read IMMU TLB Data Access Register.

Parameters:
entry TLB Entry index.
Returns:
Current value of specified IMMU TLB Data Access Register.

Definition at line 179 of file tlb.h.

References ASI_ITLB_DATA_ACCESS_REG, asi_u64_read(), tlb_data_access_addr::tlb_entry, and tlb_data_access_addr::value.

Referenced by tlb_invalidate_all(), and tlb_print().

Here is the call graph for this function:

static void itlb_data_access_write (  index_t  entry,
__u64  value
)  [static]
 

Write IMMU TLB Data Access Register.

Parameters:
entry TLB Entry index.
value Value to be written.

Definition at line 193 of file tlb.h.

References ASI_ITLB_DATA_ACCESS_REG, asi_u64_write(), flush(), tlb_data_access_addr::tlb_entry, and tlb_data_access_addr::value.

Referenced by tlb_invalidate_all().

Here is the call graph for this function:

static void itlb_data_in_write (  __u64  v  )  [static]
 

Write IMMU TLB Data in Register.

Parameters:
v Value to be written.

Definition at line 306 of file tlb.h.

References ASI_ITLB_DATA_IN_REG, asi_u64_write(), and flush().

Referenced by tlb_arch_init().

Here is the call graph for this function:

static void itlb_demap (  int  type,
int  context_encoding,
__address  page
)  [static]
 

Perform IMMU TLB Demap Operation.

Parameters:
type Selects between context and page demap.
context_encoding Specifies which Context register has Context ID for demap.
page Address which is on the page to be demapped.

Definition at line 375 of file tlb.h.

References ASI_IMMU_DEMAP, asi_u64_write(), tlb_demap_addr::context, flush(), tlb_demap_addr::type, tlb_demap_addr::value, and tlb_demap_addr::vpn.

Referenced by tlb_arch_init(), tlb_invalidate_asid(), and tlb_invalidate_pages().

Here is the call graph for this function:

static __u64 itlb_sfsr_read (  void   )  [static]
 

Read ITLB Synchronous Fault Status Register.

Returns:
Current content of I-SFSR register.

Definition at line 326 of file tlb.h.

References ASI_IMMU, asi_u64_read(), and VA_IMMU_SFSR.

Here is the call graph for this function:

static void itlb_sfsr_write (  __u64  v  )  [static]
 

Write ITLB Synchronous Fault Status Register.

Parameters:
v New value of I-SFSR register.

Definition at line 335 of file tlb.h.

References ASI_IMMU, asi_u64_write(), flush(), and VA_IMMU_SFSR.

Here is the call graph for this function:

static __u64 itlb_tag_access_read (  void   )  [static]
 

Read IMMU TLB Tag Access Register.

Returns:
Current value of IMMU TLB Tag Access Register.

Definition at line 277 of file tlb.h.

References ASI_IMMU, asi_u64_read(), and VA_IMMU_TAG_ACCESS.

Here is the call graph for this function:

static void itlb_tag_access_write (  __u64  v  )  [static]
 

Write IMMU TLB Tag Access Register.

Parameters:
v Value to be written.

Definition at line 267 of file tlb.h.

References ASI_IMMU, asi_u64_write(), flush(), and VA_IMMU_TAG_ACCESS.

Referenced by tlb_arch_init(), and tlb_invalidate_all().

Here is the call graph for this function:

static __u64 itlb_tag_read_read (  index_t  entry  )  [static]
 

Read IMMU TLB Tag Read Register.

Parameters:
entry TLB Entry index.
Returns:
Current value of specified IMMU TLB Tag Read Register.

Definition at line 239 of file tlb.h.

References ASI_ITLB_TAG_READ_REG, asi_u64_read(), tlb_data_access_addr::tlb_entry, and tlb_data_access_addr::value.

Referenced by tlb_invalidate_all(), and tlb_print().

Here is the call graph for this function:

static __u64 mmu_primary_context_read (  void   )  [static]
 

Read MMU Primary Context Register.

Returns:
Current value of Primary Context Register.

Definition at line 139 of file tlb.h.

References ASI_DMMU, asi_u64_read(), and VA_PRIMARY_CONTEXT_REG.

Here is the call graph for this function:

static void mmu_primary_context_write (  __u64  v  )  [static]
 

Write MMU Primary Context Register.

Parameters:
v New value of Primary Context Register.

Definition at line 148 of file tlb.h.

References ASI_DMMU, asi_u64_write(), flush(), and VA_PRIMARY_CONTEXT_REG.

Here is the call graph for this function:

static __u64 mmu_secondary_context_read (  void   )  [static]
 

Read MMU Secondary Context Register.

Returns:
Current value of Secondary Context Register.

Definition at line 158 of file tlb.h.

References ASI_DMMU, asi_u64_read(), and VA_SECONDARY_CONTEXT_REG.

Here is the call graph for this function:

static void mmu_secondary_context_write (  __u64  v  )  [static]
 

Write MMU Primary Context Register.

Parameters:
v New value of Primary Context Register.

Definition at line 167 of file tlb.h.

References ASI_DMMU, asi_u64_write(), flush(), and VA_PRIMARY_CONTEXT_REG.

Here is the call graph for this function:

void page_arch_init (  void   ) 
 

Definition at line 42 of file page.c.

References ht_mapping_operations.

Referenced by page_init().

void tlb_arch_init (  void   ) 
 

Initialize ITLB and DTLB.

The goal of this function is to disable MMU so that both TLBs can be purged and new kernel 4M locked entry can be installed. After TLB is initialized, MMU is enabled again.

Switching MMU off imposes the requirement for the kernel to run in identity mapped environment.

Definition at line 71 of file tlb.c.

References ASID_KERNEL, config_t::base, config, tte_data::cp, tte_data::cv, dmmu_disable, dmmu_enable, dtlb_data_in_write(), dtlb_demap(), dtlb_tag_access_write(), tte_data::g, immu_disable, immu_enable, itlb_data_in_write(), itlb_demap(), itlb_tag_access_write(), tte_data::l, tte_data::p, PAGESIZE_4M, tte_data::pfn, tte_data::size, TLB_DEMAP_CONTEXT, TLB_DEMAP_NUCLEUS, tlb_invalidate_all(), trap_switch_trap_table(), tte_data::v, tte_data::value, tlb_tag_read_reg::value, tlb_tag_read_reg::vpn, and tte_data::w.

Referenced by tlb_init().

Here is the call graph for this function:

void tlb_invalidate_all (  void   ) 
 

Invalidate all unlocked ITLB and DTLB entries.

Definition at line 226 of file tlb.c.

References itlb_data_access_read(), itlb_data_access_write(), ITLB_ENTRY_COUNT, itlb_tag_access_write(), itlb_tag_read_read(), tte_data::l, tte_data::v, tlb_tag_read_reg::value, and tte_data::value.

Referenced by tlb_arch_init(), and tlb_shootdown_ipi_recv().

Here is the call graph for this function:

void tlb_invalidate_asid (  asid_t  asid  ) 
 

Invalidate all ITLB and DTLB entries that belong to specified ASID (Context).

Parameters:
asid Address Space ID.

Definition at line 258 of file tlb.c.

References dtlb_demap(), itlb_demap(), TLB_DEMAP_CONTEXT, and TLB_DEMAP_NUCLEUS.

Referenced by asid_get(), and tlb_shootdown_ipi_recv().

Here is the call graph for this function:

void tlb_invalidate_pages (  asid_t  asid,
__address  page,
count_t  cnt
) 
 

Invalidate all ITLB and DTLB entries for specified page range in specified address space.

Parameters:
asid Address Space ID.
page First page which to sweep out from ITLB and DTLB.
cnt Number of ITLB and DTLB entries to invalidate.

Definition at line 271 of file tlb.c.

References dtlb_demap(), itlb_demap(), PAGE_SIZE, TLB_DEMAP_NUCLEUS, and TLB_DEMAP_PAGE.

Referenced by tlb_shootdown_ipi_recv().

Here is the call graph for this function:

void tlb_print (  void   ) 
 

Print contents of both TLBs.

Definition at line 199 of file tlb.c.

References tlb_tag_read_reg::context, tte_data::cp, tte_data::cv, tte_data::diag, tte_data::e, tte_data::g, tte_data::ie, itlb_data_access_read(), ITLB_ENTRY_COUNT, itlb_tag_read_read(), tte_data::l, tte_data::nfo, tte_data::p, tte_data::pfn, printf(), tte_data::size, tte_data::soft, tte_data::soft2, tte_data::v, tlb_tag_read_reg::value, tte_data::value, tlb_tag_read_reg::vpn, and tte_data::w.

Referenced by cmd_tlb().

Here is the call graph for this function:

Variable Documentation

char* context_encoding[]
 

Initial value:

 {
        "Primary",
        "Secondary",
        "Nucleus",
        "Reserved"
}

Definition at line 53 of file tlb.c.

Generated on Sun Jun 18 17:45:20 2006 for HelenOS Kernel (sparc64) by  doxygen 1.4.6