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00035 #ifndef __sparc64_ASM_H__
00036 #define __sparc64_ASM_H__
00037
00038 #include <typedefs.h>
00039 #include <arch/types.h>
00040 #include <arch/register.h>
00041 #include <config.h>
00042
00047 static inline __u64 pstate_read(void)
00048 {
00049 __u64 v;
00050
00051 __asm__ volatile ("rdpr %%pstate, %0\n" : "=r" (v));
00052
00053 return v;
00054 }
00055
00060 static inline void pstate_write(__u64 v)
00061 {
00062 __asm__ volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
00063 }
00064
00069 static inline __u64 tick_compare_read(void)
00070 {
00071 __u64 v;
00072
00073 __asm__ volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));
00074
00075 return v;
00076 }
00077
00082 static inline void tick_compare_write(__u64 v)
00083 {
00084 __asm__ volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
00085 }
00086
00091 static inline __u64 tick_read(void)
00092 {
00093 __u64 v;
00094
00095 __asm__ volatile ("rdpr %%tick, %0\n" : "=r" (v));
00096
00097 return v;
00098 }
00099
00104 static inline void tick_write(__u64 v)
00105 {
00106 __asm__ volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));
00107 }
00108
00113 static inline __u64 softint_read(void)
00114 {
00115 __u64 v;
00116
00117 __asm__ volatile ("rd %%softint, %0\n" : "=r" (v));
00118
00119 return v;
00120 }
00121
00126 static inline void softint_write(__u64 v)
00127 {
00128 __asm__ volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));
00129 }
00130
00137 static inline void clear_softint_write(__u64 v)
00138 {
00139 __asm__ volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));
00140 }
00141
00149 static inline ipl_t interrupts_enable(void) {
00150 pstate_reg_t pstate;
00151 __u64 value;
00152
00153 value = pstate_read();
00154 pstate.value = value;
00155 pstate.ie = true;
00156 pstate_write(pstate.value);
00157
00158 return (ipl_t) value;
00159 }
00160
00168 static inline ipl_t interrupts_disable(void) {
00169 pstate_reg_t pstate;
00170 __u64 value;
00171
00172 value = pstate_read();
00173 pstate.value = value;
00174 pstate.ie = false;
00175 pstate_write(pstate.value);
00176
00177 return (ipl_t) value;
00178 }
00179
00186 static inline void interrupts_restore(ipl_t ipl) {
00187 pstate_reg_t pstate;
00188
00189 pstate.value = pstate_read();
00190 pstate.ie = ((pstate_reg_t) ipl).ie;
00191 pstate_write(pstate.value);
00192 }
00193
00200 static inline ipl_t interrupts_read(void) {
00201 return (ipl_t) pstate_read();
00202 }
00203
00210 static inline __address get_stack_base(void)
00211 {
00212 __address v;
00213
00214 __asm__ volatile ("and %%sp, %1, %0\n" : "=r" (v) : "r" (~(STACK_SIZE-1)));
00215
00216 return v;
00217 }
00218
00223 static inline __u64 ver_read(void)
00224 {
00225 __u64 v;
00226
00227 __asm__ volatile ("rdpr %%ver, %0\n" : "=r" (v));
00228
00229 return v;
00230 }
00231
00236 static inline __u64 tba_read(void)
00237 {
00238 __u64 v;
00239
00240 __asm__ volatile ("rdpr %%tba, %0\n" : "=r" (v));
00241
00242 return v;
00243 }
00244
00249 static inline __u64 tpc_read(void)
00250 {
00251 __u64 v;
00252
00253 __asm__ volatile ("rdpr %%tpc, %0\n" : "=r" (v));
00254
00255 return v;
00256 }
00257
00262 static inline __u64 tl_read(void)
00263 {
00264 __u64 v;
00265
00266 __asm__ volatile ("rdpr %%tl, %0\n" : "=r" (v));
00267
00268 return v;
00269 }
00270
00275 static inline void tba_write(__u64 v)
00276 {
00277 __asm__ volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
00278 }
00279
00287 static inline __u64 asi_u64_read(asi_t asi, __address va)
00288 {
00289 __u64 v;
00290
00291 __asm__ volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" (asi));
00292
00293 return v;
00294 }
00295
00302 static inline void asi_u64_write(asi_t asi, __address va, __u64 v)
00303 {
00304 __asm__ volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" (asi) : "memory");
00305 }
00306
00307
00308
00309 void cpu_halt(void);
00310 void cpu_sleep(void);
00311 void asm_delay_loop(__u32 t);
00312
00313 #endif
00314