Changeset ee06f2a in mainline for kernel/arch/ia32/src/drivers/i8254.c

Timestamp:

2009-02-15T15:28:00Z (15 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

2d96f4d

Parents:

e7f2ad68

Message:

Introduce a more platform-neutral name for programmed I/O.

The new API looks like pio_read_n() or pio_write_n(), where n is 8, 16 or 32.
The old API (i.e. inb(), inw(), inl(), outb() outw(), outl()) may have made
some people think that the interface is only to be used with the separate I/O
space. That's not the case. This API is to be implemented on all platforms
so that we can finally have really generic kernel device drivers.

File:

• kernel/arch/ia32/src/drivers/i8254.c (modified) (2 diffs)

kernel/arch/ia32/src/drivers/i8254.c

@@ -95 +95 @@
 void i8254_normal_operation(void)
 {
-        outb(CLK_PORT4, 0x36);
+        pio_write_8(CLK_PORT4, 0x36);
         pic_disable_irqs(1 << IRQ_CLK);
-        outb(CLK_PORT1, (CLK_CONST / HZ) & 0xf);
-        outb(CLK_PORT1, (CLK_CONST / HZ) >> 8);
+        pio_write_8(CLK_PORT1, (CLK_CONST / HZ) & 0xf);
+        pio_write_8(CLK_PORT1, (CLK_CONST / HZ) >> 8);
         pic_enable_irqs(1 << IRQ_CLK);
 }
@@ -115 +115 @@
          * MAGIC_NUMBER is the magic value for 1ms.
          */
-        outb(CLK_PORT4, 0x30);
-        outb(CLK_PORT1, 0xff);
-        outb(CLK_PORT1, 0xff);
+        pio_write_8(CLK_PORT4, 0x30);
+        pio_write_8(CLK_PORT1, 0xff);
+        pio_write_8(CLK_PORT1, 0xff);
 
         do {
                 /* will read both status and count */
-                outb(CLK_PORT4, 0xc2);
-                not_ok = (uint8_t) ((inb(CLK_PORT1) >> 6) & 1);
-                t1 = inb(CLK_PORT1);
-                t1 |= inb(CLK_PORT1) << 8;
+                pio_write_8(CLK_PORT4, 0xc2);
+                not_ok = (uint8_t) ((pio_read_8(CLK_PORT1) >> 6) & 1);
+                t1 = pio_read_8(CLK_PORT1);
+                t1 |= pio_read_8(CLK_PORT1) << 8;
         } while (not_ok);
 
         asm_delay_loop(LOOPS);
 
-        outb(CLK_PORT4, 0xd2);
-        t2 = inb(CLK_PORT1);
-        t2 |= inb(CLK_PORT1) << 8;
+        pio_write_8(CLK_PORT4, 0xd2);
+        t2 = pio_read_8(CLK_PORT1);
+        t2 |= pio_read_8(CLK_PORT1) << 8;
 
         /*
          * We want to determine the overhead of the calibrating mechanism.
          */
-        outb(CLK_PORT4, 0xd2);
-        o1 = inb(CLK_PORT1);
-        o1 |= inb(CLK_PORT1) << 8;
+        pio_write_8(CLK_PORT4, 0xd2);
+        o1 = pio_read_8(CLK_PORT1);
+        o1 |= pio_read_8(CLK_PORT1) << 8;
 
         asm_fake_loop(LOOPS);
 
-        outb(CLK_PORT4, 0xd2);
-        o2 = inb(CLK_PORT1);
-        o2 |= inb(CLK_PORT1) << 8;
+        pio_write_8(CLK_PORT4, 0xd2);
+        o2 = pio_read_8(CLK_PORT1);
+        o2 |= pio_read_8(CLK_PORT1) << 8;
 
         CPU->delay_loop_const =