Changeset edebc15c in mainline for kernel/arch/mips32/src/mm/tlb.c

Timestamp:

2008-07-27T03:50:53Z (16 years ago)

Author:

Martin Decky <martin@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

4541ae4

Parents:

5e8ddf5

Message:

physical memory detection in MSIM (discontinous regions supported)
remove Sgi Indy (ARC) support — it was unmaintaned, untested for years and without uspace support

File:

• kernel/arch/mips32/src/mm/tlb.c (modified) (10 diffs)

kernel/arch/mips32/src/mm/tlb.c

@@ -54 +54 @@
 static pte_t *find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate, int *pfrc);
 
-static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, uintptr_t pfn);
-static void prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr);
-
 /** Initialize TLB
  *
@@ -77 +74 @@
                 tlbwi();
         }
-
                 
         /*
@@ -132 +128 @@
         pte->a = 1;
 
-        prepare_entry_hi(&hi, asid, badvaddr);
-        prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);
+        tlb_prepare_entry_hi(&hi, asid, badvaddr);
+        tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);
 
         /*
@@ -179 +175 @@
          */
         hi.value = cp0_entry_hi_read();
-        prepare_entry_hi(&hi, hi.asid, badvaddr);
+        tlb_prepare_entry_hi(&hi, hi.asid, badvaddr);
         cp0_entry_hi_write(hi.value);
         tlbp();
@@ -222 +218 @@
         pte->a = 1;
 
-        prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);
+        tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->d, pte->cacheable, pte->pfn);
 
         /*
@@ -263 +259 @@
          */
         hi.value = cp0_entry_hi_read();
-        prepare_entry_hi(&hi, hi.asid, badvaddr);
+        tlb_prepare_entry_hi(&hi, hi.asid, badvaddr);
         cp0_entry_hi_write(hi.value);
         tlbp();
@@ -313 +309 @@
         pte->d = 1;
 
-        prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable, pte->pfn);
+        tlb_prepare_entry_lo(&lo, pte->g, pte->p, pte->w, pte->cacheable, pte->pfn);
 
         /*
@@ -446 +442 @@
 }
 
-void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, uintptr_t pfn)
+void tlb_prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, uintptr_t pfn)
 {
         lo->value = 0;
@@ -456 +452 @@
 }
 
-void prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr)
+void tlb_prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr)
 {
         hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2);
@@ -586 +582 @@
         for (i = 0; i < cnt + 1; i += 2) {
                 hi.value = 0;
-                prepare_entry_hi(&hi, asid, page + i * PAGE_SIZE);
+                tlb_prepare_entry_hi(&hi, asid, page + i * PAGE_SIZE);
                 cp0_entry_hi_write(hi.value);