Ignore:
Timestamp:
2006-09-14T13:07:32Z (18 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
06e1e95
Parents:
775df25
Message:

When creating TLB mapping for the sparc64 kernel, enable CV (cacheable virtually) bit.
Also install locked mappings only in context 0.

File:
1 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/sparc64/include/trap/mmu.h

    r775df25 re5ecc02  
    8686        bz 0f                                           ! page address is zero
    8787
    88         or %g3, (TTE_CP|TTE_P|TTE_W), %g2               ! 8K pages are the default (encoded as 0)
     88        or %g3, (TTE_CV|TTE_CP|TTE_P|TTE_W), %g2        ! 8K pages are the default (encoded as 0)
    8989        mov 1, %g3
    9090        sllx %g3, TTE_V_SHIFT, %g3
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