Changeset e08162b in mainline for kernel/arch/sparc64/src/mm/sun4u/tsb.c

Timestamp:

2016-01-07T13:41:38Z (8 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

f4582c6

Parents:

7254df6

Message:

sparc64: TSB needs to be naturally aligned

The ITSB and DTSB on sun4u and the TSB on sun4v are mapped by a single
64K page, so they need to be aligned to 64K. Moreover, the TSB pointer
contruction demands the natural alignment: 32K for ITSB/DTSB on sun4u
and 64K for the unified TSB on sun4v.

The code was also streamlined and made more beautiful.

File:

• kernel/arch/sparc64/src/mm/sun4u/tsb.c (modified) (11 diffs)

kernel/arch/sparc64/src/mm/sun4u/tsb.c

@@ -42 +42 @@
 #include <debug.h>
 
-#define TSB_INDEX_MASK  ((1 << (21 + 1 + TSB_SIZE - MMU_PAGE_WIDTH)) - 1)
-
 /** Invalidate portion of TSB.
  *
@@ -60 +58 @@
         size_t cnt;
         
-        ASSERT(as->arch.itsb && as->arch.dtsb);
+        ASSERT(as->arch.itsb);
+        ASSERT(as->arch.dtsb);
         
-        i0 = (page >> MMU_PAGE_WIDTH) & TSB_INDEX_MASK;
-        ASSERT(i0 < ITSB_ENTRY_COUNT && i0 < DTSB_ENTRY_COUNT);
+        i0 = (page >> MMU_PAGE_WIDTH) & ITSB_ENTRY_MASK;
 
         if (pages == (size_t) -1 || (pages * 2) > ITSB_ENTRY_COUNT)
@@ -71 +69 @@
         
         for (i = 0; i < cnt; i++) {
-                as->arch.itsb[(i0 + i) & (ITSB_ENTRY_COUNT - 1)].tag.invalid =
-                    true;
-                as->arch.dtsb[(i0 + i) & (DTSB_ENTRY_COUNT - 1)].tag.invalid =
-                    true;
+                as->arch.itsb[(i0 + i) & ITSB_ENTRY_MASK].tag.invalid = true;
+                as->arch.dtsb[(i0 + i) & DTSB_ENTRY_MASK].tag.invalid = true;
         }
 }
@@ -86 +82 @@
 {
         as_t *as;
-        tsb_entry_t *tsb;
+        tsb_entry_t *tte;
         size_t entry;
 
@@ -92 +88 @@
         
         as = t->as;
-        entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK; 
-        ASSERT(entry < ITSB_ENTRY_COUNT);
-        tsb = &as->arch.itsb[entry];
+        entry = ((t->page >> MMU_PAGE_WIDTH) + index) & ITSB_ENTRY_MASK;
+        tte = &as->arch.itsb[entry];
 
         /*
@@ -102 +97 @@
          */
 
-        tsb->tag.invalid = true;        /* invalidate the entry
+        tte->tag.invalid = true;        /* invalidate the entry
                                          * (tag target has this
                                          * set to 0) */
@@ -108 +103 @@
         write_barrier();
 
-        tsb->tag.context = as->asid;
+        tte->tag.context = as->asid;
         /* the shift is bigger than PAGE_WIDTH, do not bother with index  */
-        tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
-        tsb->data.value = 0;
-        tsb->data.size = PAGESIZE_8K;
-        tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
-        tsb->data.cp = t->c;    /* cp as cache in phys.-idxed, c as cacheable */
-        tsb->data.p = t->k;     /* p as privileged, k as kernel */
-        tsb->data.v = t->p;     /* v as valid, p as present */
+        tte->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
+        tte->data.value = 0;
+        tte->data.size = PAGESIZE_8K;
+        tte->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
+        tte->data.cp = t->c;    /* cp as cache in phys.-idxed, c as cacheable */
+        tte->data.p = t->k;     /* p as privileged, k as kernel */
+        tte->data.v = t->p;     /* v as valid, p as present */
         
         write_barrier();
         
-        tsb->tag.invalid = false;       /* mark the entry as valid */
+        tte->tag.invalid = false;       /* mark the entry as valid */
 }
 
@@ -132 +127 @@
 {
         as_t *as;
-        tsb_entry_t *tsb;
+        tsb_entry_t *tte;
         size_t entry;
         
@@ -138 +133 @@
 
         as = t->as;
-        entry = ((t->page >> MMU_PAGE_WIDTH) + index) & TSB_INDEX_MASK;
-        ASSERT(entry < DTSB_ENTRY_COUNT);
-        tsb = &as->arch.dtsb[entry];
+        entry = ((t->page >> MMU_PAGE_WIDTH) + index) & DTSB_ENTRY_MASK;
+        tte = &as->arch.dtsb[entry];
 
         /*
@@ -148 +142 @@
          */
 
-        tsb->tag.invalid = true;        /* invalidate the entry
+        tte->tag.invalid = true;        /* invalidate the entry
                                          * (tag target has this
                                          * set to 0) */
@@ -154 +148 @@
         write_barrier();
 
-        tsb->tag.context = as->asid;
+        tte->tag.context = as->asid;
         /* the shift is bigger than PAGE_WIDTH, do not bother with index */
-        tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
-        tsb->data.value = 0;
-        tsb->data.size = PAGESIZE_8K;
-        tsb->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
-        tsb->data.cp = t->c;
+        tte->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
+        tte->data.value = 0;
+        tte->data.size = PAGESIZE_8K;
+        tte->data.pfn = (t->frame >> MMU_FRAME_WIDTH) + index;
+        tte->data.cp = t->c;
 #ifdef CONFIG_VIRT_IDX_DCACHE
-        tsb->data.cv = t->c;
+        tte->data.cv = t->c;
 #endif /* CONFIG_VIRT_IDX_DCACHE */
-        tsb->data.p = t->k;             /* p as privileged */
-        tsb->data.w = ro ? false : t->w;
-        tsb->data.v = t->p;
+        tte->data.p = t->k;             /* p as privileged */
+        tte->data.w = ro ? false : t->w;
+        tte->data.v = t->p;
         
         write_barrier();
         
-        tsb->tag.invalid = false;       /* mark the entry as valid */
+        tte->tag.invalid = false;       /* mark the entry as valid */
 }