Changeset dea75c04 in mainline


Ignore:
Timestamp:
2011-10-03T18:31:57Z (12 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
d2134da
Parents:
f451dae
Message:

sb16: Add register value interpretation.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • uspace/drv/audio/sb16/dma_controller.c

    rf451dae rdea75c04  
    4949
    5050        uint8_t command_status;
    51         uint8_t request;
     51#define DMA_STATUS_REQ(x) (1 << ((x % 4) + 4))
     52#define DMA_STATUS_COMPLETE(x) (1 << (x % 4))
     53/* http://wiki.osdev.org/DMA: The only bit that works is COND(bit 2) */
     54#define DMA_COMMAND_COND (1 << 2) /* Disables DMA controller */
     55
     56        uint8_t request; /* Memory to memory transfers, NOT implemented on PCs*/
    5257        uint8_t single_mask;
     58#define DMA_SINGLE_MASK_CHAN_SELECT_MASK (0x3)
     59#define DMA_SINGLE_MASK_CHAN_SELECT_SHIFT (0)
     60#define DMA_SINGLE_MASK_MASK_ON_FLAG (1 << 2)
     61
    5362        uint8_t mode;
     63#define DMA_MODE_CHAN_SELECT_MASK (0x3)
     64#define DMA_MODE_CHAN_SELECT_SHIFT (0)
     65#define DMA_MODE_CHAN_TRA_MASK (0x3)
     66#define DMA_MODE_CHAN_TRA_SHIFT (2)
     67#define DMA_MODE_CHAN_TRA_SELF_TEST (0)
     68#define DMA_MODE_CHAN_TRA_WRITE (1)
     69#define DMA_MODE_CHAN_TRA_READ (2)
     70#define DMA_MODE_CHAN_AUTO_FLAG (1 << 4)
     71#define DMA_MODE_CHAN_DOWN_FLAG (1 << 5)
     72#define DMA_MODE_CHAN_MOD_MASK (0x3)
     73#define DMA_MODE_CHAN_MOD_SHIFT (6)
     74#define DMA_MODE_CHAN_MOD_DEMAND (0)
     75#define DMA_MODE_CHAN_MOD_SINGLE (1)
     76#define DMA_MODE_CHAN_MOD_BLOCK (2)
     77#define DMA_MODE_CHAN_MOD_CASCADE (3)
     78
    5479        uint8_t flip_flop;
    55         uint8_t master_reset_intermediate;
     80        uint8_t master_reset; /* Intermediate is not implemented on PCs */
     81        uint8_t mask_reset;
     82/* Master reset sets Flip-Flop low, clears status,sets all mask bits on */
     83
    5684        uint8_t multi_mask;
     85#define DMA_MULTI_MASK_CHAN(x) (1 << (x % 4))
     86
    5787} dma_controller_regs_first_t;
    5888
    5989#define DMA_CONTROLLER_SECOND_BASE 0xc0
     90/* See dma_controller_regs_first_t for register values */
    6091typedef struct dma_controller_regs_second {
    6192        uint8_t channel_start4;
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