Changeset f451dae in mainline


Ignore:
Timestamp:
2011-10-03T17:58:31Z (13 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
dea75c04
Parents:
84dec070
Message:

sb16: Add 8237 DMA Controller registers.

Ugly as hell…

File:
1 edited

Legend:

Unmodified
Added
Removed

  • uspace/drv/audio/sb16/dma_controller.c

    r84dec070 rf451dae  
    3737#include "dma_controller.h"
    3838
     39#define DMA_CONTROLLER_FIRST_BASE 0x0
     40typedef struct dma_controller_regs_first {
     41        uint8_t channel_start0;
     42        uint8_t channel_count0;
     43        uint8_t channel_start1;
     44        uint8_t channel_count1;
     45        uint8_t channel_start2;
     46        uint8_t channel_count2;
     47        uint8_t channel_start3;
     48        uint8_t channel_count3;
     49
     50        uint8_t command_status;
     51        uint8_t request;
     52        uint8_t single_mask;
     53        uint8_t mode;
     54        uint8_t flip_flop;
     55        uint8_t master_reset_intermediate;
     56        uint8_t multi_mask;
     57} dma_controller_regs_first_t;
     58
     59#define DMA_CONTROLLER_SECOND_BASE 0xc0
     60typedef struct dma_controller_regs_second {
     61        uint8_t channel_start4;
     62        uint8_t reserved0;
     63        uint8_t channel_count4;
     64        uint8_t reserved1;
     65        uint8_t channel_start5;
     66        uint8_t reserved2;
     67        uint8_t channel_count5;
     68        uint8_t reserved3;
     69        uint8_t channel_start6;
     70        uint8_t reserved4;
     71        uint8_t channel_count6;
     72        uint8_t reserved5;
     73        uint8_t channel_start7;
     74        uint8_t reserved6;
     75        uint8_t channel_count7;
     76
     77        uint8_t command_status;
     78        uint8_t reserved8;
     79        uint8_t request;
     80        uint8_t reserved9;
     81        uint8_t single_mask;
     82        uint8_t reserveda;
     83        uint8_t mode;
     84        uint8_t reservedb;
     85        uint8_t flip_flop;
     86        uint8_t reservedc;
     87        uint8_t master_reset_intermediate;
     88        uint8_t reservedd;
     89        uint8_t multi_mask;
     90} dma_controller_regs_second_t;
     91
     92#define DMA_CONTROLLER_PAGE_BASE 0x81
     93typedef struct dma_page_regs {
     94        uint8_t channel2;
     95        uint8_t channel3;
     96        uint8_t channel1;
     97        uint8_t reserved0;
     98        uint8_t reserved1;
     99        uint8_t reserved2;
     100        uint8_t channel0;
     101        uint8_t reserved3;
     102        uint8_t channel6;
     103        uint8_t channel7;
     104        uint8_t channel5;
     105        uint8_t reserved4;
     106        uint8_t reserved5;
     107        uint8_t reserved6;
     108        uint8_t channel4;
     109} dma_page_regs_t;
     110
     111typedef struct dma_channel {
     112        uint8_t offset_reg_address;
     113        uint8_t size_reg_address;
     114        uint8_t page_reg_address;
     115} dma_channel_t;
     116
     117typedef struct dma_controller {
     118        dma_channel_t channel[8];
     119        dma_page_regs_t *page_table;
     120        dma_controller_regs_first_t *first;
     121        dma_controller_regs_second_t *second;
     122} dma_controller_t;
     123
     124dma_controller_t controller_8237 = {
     125        .channel = {
     126            { 0x00, 0x01, 0x87 }, { 0x02, 0x03, 0x83 },
     127            { 0x04, 0x05, 0x81 }, { 0x06, 0x07, 0x82 },
     128            { 0xc0, 0xc2, 0x8f }, { 0xc4, 0xc6, 0x8b },
     129            { 0xc8, 0xca, 0x89 }, { 0xcc, 0xce, 0x8a } },
     130        .page_table = NULL,
     131        .first = NULL,
     132        .second = NULL,
     133};
     134
     135static inline dma_controller_t *dma_controller_init()
     136{
     137        return NULL;
     138}
     139/*----------------------------------------------------------------------------*/
    39140int dma_setup_channel(unsigned channel, uintptr_t pa, size_t size)
    40141{
     142        static dma_controller_t *controller = NULL;
     143        if (!controller)
     144                return EIO;
    41145        return ENOTSUP;
    42146}
    43 
    44147/**
    45148 * @}
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