Changeset de36fdd in mainline
 Timestamp:
 20130106T19:52:43Z (9 years ago)
 Branches:
 lfn, master
 Children:
 b4b3a4cb
 Parents:
 664fd6d5
 Location:
 kernel/arch/arm32
 Files:

 1 added
 2 edited
Legend:
 Unmodified
 Added
 Removed

kernel/arch/arm32/Makefile.inc
r664fd6d5 rde36fdd 38 38 # This is necessary to allow vmsr insn and fpexc manipulation 39 39 # Use vfp32 to allow context save/restore of d16d31 regs. 40 GCC_CFLAGS += mfloatabi=hard mfpu=vfp340 AFLAGS += mfloatabi=hard mfpu=vfp3 41 41 endif 42 42 … … 70 70 ifeq ($(CONFIG_FPU),y) 71 71 ARCH_SOURCES += arch/$(KARCH)/src/fpu_context.c 72 ARCH_SOURCES += arch/$(KARCH)/src/fpu.s 72 73 endif 73 74 
kernel/arch/arm32/src/fpu_context.c
r664fd6d5 rde36fdd 103 103 }; 104 104 105 static inline uint32_t fpscr_read() 106 { 107 uint32_t reg; 108 asm volatile ( 109 "vmrs %0, fpscr\n" 110 :"=r" (reg):: 111 ); 112 return reg; 113 } 114 115 static inline void fpscr_write(uint32_t val) 116 { 117 asm volatile ( 118 "vmsr fpscr, %0\n" 119 ::"r" (val): 120 ); 121 } 122 123 static inline uint32_t fpexc_read() 124 { 125 uint32_t reg; 126 asm volatile ( 127 "vmrs %0, fpexc\n" 128 :"=r" (reg):: 129 ); 130 return reg; 131 } 132 133 static inline void fpexc_write(uint32_t val) 134 { 135 asm volatile ( 136 "vmsr fpexc, %0\n" 137 ::"r" (val): 138 ); 139 } 105 extern uint32_t fpsid_read(void); 106 extern uint32_t mvfr0_read(void); 107 extern uint32_t fpscr_read(void); 108 extern void fpscr_write(uint32_t); 109 extern uint32_t fpexc_read(void); 110 extern void fpexc_write(uint32_t); 111 112 extern void fpu_context_save_s32(fpu_context_t *); 113 extern void fpu_context_restore_s32(fpu_context_t *); 114 extern void fpu_context_save_d16(fpu_context_t *); 115 extern void fpu_context_restore_d16(fpu_context_t *); 116 extern void fpu_context_save_d32(fpu_context_t *); 117 extern void fpu_context_restore_d32(fpu_context_t *); 140 118 141 119 static void (*save_context)(fpu_context_t *ctx); 142 120 static void (*restore_context)(fpu_context_t *ctx); 143 144 /** Saves 32 single precision fpu registers.145 * @param ctx FPU context area.146 * Used by VFPv1147 */148 static void fpu_context_save_s32(fpu_context_t *ctx)149 {150 asm volatile (151 "vmrs r1, fpexc\n"152 "vmrs r2, fpscr\n"153 "stmia %0!, {r1, r2}\n"154 "vstmia %0!, {s0s31}\n"155 ::"r" (ctx): "r1","r2","memory"156 );157 }158 159 /** Restores 32 single precision fpu registers.160 * @param ctx FPU context area.161 * Used by VFPv1162 */163 static void fpu_context_restore_s32(fpu_context_t *ctx)164 {165 asm volatile (166 "ldmia %0!, {r1, r2}\n"167 "vmsr fpexc, r1\n"168 "vmsr fpscr, r2\n"169 "vldmia %0!, {s0s31}\n"170 ::"r" (ctx): "r1","r2"171 );172 }173 174 /** Saves 16 double precision fpu registers.175 * @param ctx FPU context area.176 * Used by VFPv2, VFPv3d16, and VFPv4d16.177 */178 static void fpu_context_save_d16(fpu_context_t *ctx)179 {180 asm volatile (181 "vmrs r1, fpexc\n"182 "vmrs r2, fpscr\n"183 "stmia %0!, {r1, r2}\n"184 "vstmia %0!, {d0d15}\n"185 ::"r" (ctx): "r1","r2","memory"186 );187 }188 189 /** Restores 16 double precision fpu registers.190 * @param ctx FPU context area.191 * Used by VFPv2, VFPv3d16, and VFPv4d16.192 */193 static void fpu_context_restore_d16(fpu_context_t *ctx)194 {195 asm volatile (196 "ldmia %0!, {r1, r2}\n"197 "vmsr fpexc, r1\n"198 "vmsr fpscr, r2\n"199 "vldmia %0!, {d0d15}\n"200 ::"r" (ctx): "r1","r2"201 );202 }203 204 /** Saves 32 double precision fpu registers.205 * @param ctx FPU context area.206 * Used by VFPv3d32, VFPv4d32, and advanced SIMD.207 */208 static void fpu_context_save_d32(fpu_context_t *ctx)209 {210 asm volatile (211 "vmrs r1, fpexc\n"212 "stmia %0!, {r1}\n"213 "vmrs r1, fpscr\n"214 "stmia %0!, {r1}\n"215 "vstmia %0!, {d0d15}\n"216 "vstmia %0!, {d16d31}\n"217 ::"r" (ctx): "r1","memory"218 );219 }220 221 /** Restores 32 double precision fpu registers.222 * @param ctx FPU context area.223 * Used by VFPv3d32, VFPv4d32, and advanced SIMD.224 */225 static void fpu_context_restore_d32(fpu_context_t *ctx)226 {227 asm volatile (228 "ldmia %0!, {r1}\n"229 "vmsr fpexc, r1\n"230 "ldmia %0!, {r1}\n"231 "vmsr fpscr, r1\n"232 "vldmia %0!, {d0d15}\n"233 "vldmia %0!, {d16d31}\n"234 ::"r" (ctx): "r1"235 );236 }237 121 238 122 static int fpu_have_coprocessor_access() … … 285 169 return; 286 170 287 uint32_t fpsid = 0; 288 asm volatile ( 289 "vmrs %0, fpsid\n" 290 :"=r"(fpsid):: 291 ); 171 const uint32_t fpsid = fpsid_read(); 292 172 if (fpsid & FPSID_SW_ONLY_FLAG) { 293 173 printf("No FPU avaiable\n"); … … 309 189 case FPU_VFPv3_NO_COMMON: 310 190 case FPU_VFPv3_COMMONv3: { 311 uint32_t mvfr0 = 0; 312 asm volatile ( 313 "vmrs %0,mvfr0\n" 314 :"=r"(mvfr0):: 315 ); 191 const uint32_t mvfr0 = mvfr0_read(); 316 192 /* See page B41637 */ 317 193 if ((mvfr0 & 0xf) == 0x1) {
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