Changeset 664fd6d5 in mainline

Timestamp:

2013-01-06T19:20:33Z (11 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

de36fdd

Parents:

b5a3b50

Message:

arm32: Check access to CP10 and CP11 before using fpu instructions.

File:

• kernel/arch/arm32/src/fpu_context.c (modified) (8 diffs)

kernel/arch/arm32/src/fpu_context.c

@@ -58 +58 @@
         FPEXC_EX_FLAG = (1 << 31),
         FPEXC_ENABLED_FLAG = (1 << 30),
+};
+
+/* See Architecture reference manual ch. B4.1.40 */
+enum {
+        CPACR_CP10_MASK = 0x3 << 20,
+        CPACR_CP11_MASK = 0x3 << 22,
+        CPACR_CP10_USER_ACCESS = CPACR_CP10_MASK,
+        CPACR_CP11_USER_ACCESS = CPACR_CP11_MASK,
 };
 
@@ -228 +236 @@
 }
 
+static int fpu_have_coprocessor_access()
+{
+        uint32_t cpacr;
+        asm volatile ("MRC p15, 0, %0, c1, c0, 2" :"=r" (cpacr)::);
+        /* FPU needs access to coprocessor 10 and 11.
+         * Moreover they need to have same access enabledd */
+        if (((cpacr & CPACR_CP10_MASK) == CPACR_CP10_USER_ACCESS) &&
+           ((cpacr & CPACR_CP11_MASK) == CPACR_CP11_USER_ACCESS))
+                return 1;
+
+        return 0;
+}
+
+static void fpu_enable_coprocessor_access()
+{
+        uint32_t cpacr;
+        asm volatile ("mrc p15, 0, %0, c1, c0, 2" :"=r" (cpacr)::);
+        /* FPU needs access to coprocessor 10 and 11.
+         * Moreover, they need to have same access enabled */
+        cpacr |= CPACR_CP10_USER_ACCESS;
+        cpacr |= CPACR_CP11_USER_ACCESS;
+        asm volatile ("mcr p15, 0, %0, c1, c0, 2" :"=r" (cpacr)::);
+}
+
+
 void fpu_init(void)
 {
+        /* Enable coprocessor access*/
+        fpu_enable_coprocessor_access();
+
+        /* Check if we succeeded */
+        if (!fpu_have_coprocessor_access())
+                return;
+
         /* Clear all fpu flags */
         fpexc_write(0);
@@ -241 +281 @@
 void fpu_setup(void)
 {
+        /* Check if we have access */
+        if (!fpu_have_coprocessor_access())
+                return;
+
         uint32_t fpsid = 0;
         asm volatile (
@@ -288 +332 @@
 bool handle_if_fpu_exception(void)
 {
+        /* Check if we have access */
+        if (!fpu_have_coprocessor_access())
+                return false;
+
         const uint32_t fpexc = fpexc_read();
         if (fpexc & FPEXC_ENABLED_FLAG) {
@@ -305 +353 @@
 void fpu_enable(void)
 {
+        /* Check if we have access */
+        if (!fpu_have_coprocessor_access())
+                return;
         /* Enable FPU instructions */
         fpexc_write(fpexc_read() | FPEXC_ENABLED_FLAG);
@@ -311 +362 @@
 void fpu_disable(void)
 {
+        /* Check if we have access */
+        if (!fpu_have_coprocessor_access())
+                return;
         /* Disable FPU instructions */
         fpexc_write(fpexc_read() & ~FPEXC_ENABLED_FLAG);
@@ -317 +371 @@
 void fpu_context_save(fpu_context_t *ctx)
 {
+        /* Check if we have access */
+        if (!fpu_have_coprocessor_access())
+                return;
         const uint32_t fpexc = fpexc_read();
 
@@ -329 +386 @@
 void fpu_context_restore(fpu_context_t *ctx)
 {
+        /* Check if we have access */
+        if (!fpu_have_coprocessor_access())
+                return;
         if (restore_context)
                 restore_context(ctx);