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Changeset d9ee2ea in mainline for kernel/arch/ia64/src/mm/as.c

2010-01-10T20:48:38Z (12 years ago)
Jakub Jermar <jakub@…>
lfn, master

Change the way how RIDs are mapped onto ASIDs. Instead of 7 RIDs per ASID, now
there will be 8 RIDs per one ASID. This will slightly reduce the number of
available ASIDs, but not significantly.

The kernel will now have all 8 RIDs instead of only one. RID 0 - 7 belong to the
kernel, but only RID 7 accessible from VRN 7 is actually used by the kernel.
This allows us to use RID 0 for VRN 0 and differentiate thus between
0x0000000000000000 and 0xe000000000000000 in a more elegant way. test fault1
will now associate the kernel bad trap with RID 0 which maps to ASID_KERNEL.

User tasks will also be given 8 RIDs, but will use only the lower 7 that fit
into VRN 0 - 6, because the last VRN needs to be reserved for the kernel. The
eighth RID will be unused for now. It can be used for something completely
different one day or if the task needs to establish some special mappings.

So with this change, the kernel now has a 64-bit address space compared to
previous 61 bits, but still makes use only of the highest 1/8 (i.e. 61-bits).
Applications continue to have an address space composed of 7 61-bit blocks which
are arranged in a consecutive way. Each application now has one hidden and
currently unused 61-bit segment.

1 edited


  • kernel/arch/ia64/src/mm/as.c

    r0ff9e67 rd9ee2ea  
    7070                rr.word = rr_read(i);
    7171       = false;              /* disable VHPT walker */
    72                 if (as == AS_KERNEL)
    73                = RID_INVALID;
    74                 else
    75                = ASID2RID(as->asid, i);
     72       = ASID2RID(as->asid, i);
    7673       = PAGE_WIDTH;
    7774                rr_write(i, rr.word);
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