Changeset cb0ea39 in mainline for uspace/app/lspci/libpci/i386-ports.c
- Timestamp:
- 2009-08-09T13:56:50Z (15 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 24f27bb
- Parents:
- 24edc18
- File:
-
- 1 moved
Legend:
- Unmodified
- Added
- Removed
-
uspace/app/lspci/libpci/i386-ports.c
r24edc18 rcb0ea39 10 10 11 11 #include <unistd.h> 12 #include <ddi.h> 13 #include <libarch/ddi.h> 12 14 13 15 #include "internal.h" 14 16 15 static inline void outb(u8 b, u16 port) 16 { 17 asm volatile ("outb %0, %1\n" :: "a" (b), "d" (port)); 18 } 19 20 static inline void outw(u16 w, u16 port) 21 { 22 asm volatile ("outw %0, %1\n" :: "a" (w), "d" (port)); 23 } 24 25 static inline void outl(u32 l, u16 port) 26 { 27 asm volatile ("outl %0, %1\n" :: "a" (l), "d" (port)); 28 } 29 30 static inline u8 inb(u16 port) 31 { 32 u8 val; 33 34 asm volatile ("inb %1, %0 \n" : "=a" (val) : "d"(port)); 35 return val; 36 } 37 38 static inline u16 inw(u16 port) 39 { 40 u16 val; 41 42 asm volatile ("inw %1, %0 \n" : "=a" (val) : "d"(port)); 43 return val; 44 } 45 46 static inline u32 inl(u16 port) 47 { 48 u32 val; 49 50 asm volatile ("inl %1, %0 \n" : "=a" (val) : "d"(port)); 51 return val; 52 } 17 #define PCI_CONF1 0xcf8 18 #define PCI_CONF1_SIZE 8 19 53 20 54 21 static void conf12_init(struct pci_access *a) 55 { 22 { 56 23 } 57 24 … … 80 47 for (d.dev = 0; d.dev < 32; d.dev++) { 81 48 u16 class, vendor; 82 if ( (m->read(&d, PCI_CLASS_DEVICE, (byte *) & class,49 if (m->read(&d, PCI_CLASS_DEVICE, (byte *) & class, 83 50 sizeof(class)) 84 51 && (class == cpu_to_le16(PCI_CLASS_BRIDGE_HOST) 85 || class == cpu_to_le16(PCI_CLASS_DISPLAY_VGA)) )86 || (m->read(&d, PCI_VENDOR_ID, (byte *) & vendor,52 || class == cpu_to_le16(PCI_CLASS_DISPLAY_VGA)) 53 || m->read(&d, PCI_VENDOR_ID, (byte *) & vendor, 87 54 sizeof(vendor)) 88 55 && (vendor == cpu_to_le16(PCI_VENDOR_ID_INTEL) 89 || vendor == cpu_to_le16(PCI_VENDOR_ID_COMPAQ))) ){56 || vendor == cpu_to_le16(PCI_VENDOR_ID_COMPAQ))) { 90 57 a->debug("...outside the Asylum at 0/%02x/0", 91 58 d.dev); … … 107 74 unsigned int tmp; 108 75 int res = 0; 109 110 outb(0x01, 0xCFB); 111 tmp = inl(0xCF8); 112 outl(0x80000000, 0xCF8); 113 if (inl(0xCF8) == 0x80000000) 76 77 /* 78 * Gain control over PCI configuration ports. 79 */ 80 void * addr; 81 if (pio_enable((void *)PCI_CONF1, PCI_CONF1_SIZE, &addr)) { 82 return 0; 83 } 84 85 pio_write_8(0xCFB, 0x01); 86 tmp = pio_read_32(0xCF8); 87 pio_write_32(0xCF8, 0x80000000); 88 if (pio_read_32(0xCF8) == 0x80000000) { 114 89 res = 1; 115 outl(tmp, 0xCF8); 116 if (res) 90 } 91 pio_write_32(0xCF8, tmp); 92 if (res) { 117 93 res = intel_sanity_check(a, &pm_intel_conf1); 94 } 118 95 return res; 119 96 } … … 126 103 return 0; 127 104 128 outl(0x80000000 | ((d->bus & 0xff) << 16) |129 (PCI_DEVFN(d->dev, d->func) << 8) | (pos & ~3) , 0xcf8);130 131 switch (len) { 132 case 1: 133 buf[0] = inb(addr);134 break; 135 case 2: 136 ((u16 *) buf)[0] = cpu_to_le16( inw(addr));137 break; 138 case 4: 139 ((u32 *) buf)[0] = cpu_to_le32( inl(addr));105 pio_write_32(0xcf8, 0x80000000 | ((d->bus & 0xff) << 16) | 106 (PCI_DEVFN(d->dev, d->func) << 8) | (pos & ~3)); 107 108 switch (len) { 109 case 1: 110 buf[0] = pio_read_8(addr); 111 break; 112 case 2: 113 ((u16 *) buf)[0] = cpu_to_le16(pio_read_16(addr)); 114 break; 115 case 4: 116 ((u32 *) buf)[0] = cpu_to_le32(pio_read_32(addr)); 140 117 break; 141 118 default: … … 152 129 return 0; 153 130 154 outl(0x80000000 | ((d->bus & 0xff) << 16) |155 (PCI_DEVFN(d->dev, d->func) << 8) | (pos & ~3) , 0xcf8);156 157 switch (len) { 158 case 1: 159 outb(buf[0], addr);160 break; 161 case 2: 162 outw(le16_to_cpu(((u16 *) buf)[0]), addr);163 break; 164 case 4: 165 outl(le32_to_cpu(((u32 *) buf)[0]), addr);131 pio_write_32(0xcf8, 0x80000000 | ((d->bus & 0xff) << 16) | 132 (PCI_DEVFN(d->dev, d->func) << 8) | (pos & ~3)); 133 134 switch (len) { 135 case 1: 136 pio_write_8(addr, buf[0]); 137 break; 138 case 2: 139 pio_write_16(addr, le16_to_cpu(((u16 *) buf)[0])); 140 break; 141 case 4: 142 pio_write_32(addr, le32_to_cpu(((u32 *) buf)[0])); 166 143 break; 167 144 default: … … 177 154 static int conf2_detect(struct pci_access *a) 178 155 { 156 /* 157 * Gain control over PCI configuration ports. 158 */ 159 void * addr; 160 if (pio_enable((void *)PCI_CONF1, PCI_CONF1_SIZE, &addr)) { 161 return 0; 162 } 163 if (pio_enable((void *)0xC000, 0x1000, &addr)) { 164 return 0; 165 } 166 179 167 /* This is ugly and tends to produce false positives. Beware. */ 180 outb(0x00, 0xCFB);181 outb(0x00, 0xCF8);182 outb(0x00, 0xCFA);183 if ( inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00)168 pio_write_8(0xCFB, 0x00); 169 pio_write_8(0xCF8, 0x00); 170 pio_write_8(0xCFA, 0x00); 171 if (pio_read_8(0xCF8) == 0x00 && pio_read_8(0xCFA) == 0x00) 184 172 return intel_sanity_check(a, &pm_intel_conf2); 185 173 else … … 197 185 /* conf2 supports only 16 devices per bus */ 198 186 return 0; 199 outb((d->func << 1) | 0xf0, 0xcf8);200 outb(d->bus, 0xcfa);201 switch (len) { 202 case 1: 203 buf[0] = inb(addr);204 break; 205 case 2: 206 ((u16 *) buf)[0] = cpu_to_le16( inw(addr));207 break; 208 case 4: 209 ((u32 *) buf)[0] = cpu_to_le32( inl(addr));210 break; 211 default: 212 outb(0, 0xcf8);187 pio_write_8(0xcf8, (d->func << 1) | 0xf0); 188 pio_write_8(0xcfa, d->bus); 189 switch (len) { 190 case 1: 191 buf[0] = pio_read_8(addr); 192 break; 193 case 2: 194 ((u16 *) buf)[0] = cpu_to_le16(pio_read_16(addr)); 195 break; 196 case 4: 197 ((u32 *) buf)[0] = cpu_to_le32(pio_read_32(addr)); 198 break; 199 default: 200 pio_write_8(0xcf8, 0); 213 201 return pci_generic_block_read(d, pos, buf, len); 214 202 } 215 outb(0, 0xcf8);203 pio_write_8(0xcf8, 0); 216 204 return 1; 217 205 } … … 226 214 if (d->dev >= 16) 227 215 d->access->error("conf2_write: only first 16 devices exist."); 228 outb((d->func << 1) | 0xf0, 0xcf8);229 outb(d->bus, 0xcfa);230 switch (len) { 231 case 1: 232 outb(buf[0], addr);233 break; 234 case 2: 235 outw(le16_to_cpu(*(u16 *) buf), addr);236 break; 237 case 4: 238 outl(le32_to_cpu(*(u32 *) buf), addr);239 break; 240 default: 241 outb(0, 0xcf8);216 pio_write_8(0xcf8, (d->func << 1) | 0xf0); 217 pio_write_8(0xcfa, d->bus); 218 switch (len) { 219 case 1: 220 pio_write_8(addr, buf[0]); 221 break; 222 case 2: 223 pio_write_16(addr, le16_to_cpu(*(u16 *) buf)); 224 break; 225 case 4: 226 pio_write_32(addr, le32_to_cpu(*(u32 *) buf)); 227 break; 228 default: 229 pio_write_8(0xcf8, 0); 242 230 return pci_generic_block_write(d, pos, buf, len); 243 231 } 244 outb(0, 0xcf8);232 pio_write_8(0xcf8, 0); 245 233 return 1; 246 234 }
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