Changeset c19808fd in mainline


Ignore:
Timestamp:
2013-01-23T00:11:45Z (11 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
bfb6576
Parents:
c9d0642d
Message:

arm32, barriers: Add note about availability of Cache line size information

File:
1 edited

Legend:

Unmodified
Added
Removed

  • kernel/arch/arm32/include/barrier.h

    rc9d0642d rc19808fd  
    113113        inst_barrier();              /* Wait for Inst refetch */\
    114114} while (0)
    115 //TODO would be better to use cacheline size here
     115/* @note: Cache type register is not awailable in uspace. We would need
     116 * to export the cache line value, or use syscall for uspace smc_coherence */
    116117#define smc_coherence_block(a, l) \
    117118do { \
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