Changeset bd48f4c in mainline for kernel/arch/sparc64/include/mm/sun4u/tlb.h
- Timestamp:
- 2010-07-12T10:53:30Z (14 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- bd11d3e
- Parents:
- c40e6ef (diff), bee2d4c (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the(diff)links above to see all the changes relative to each parent. - File:
-
- 1 edited
-
kernel/arch/sparc64/include/mm/sun4u/tlb.h (modified) (34 diffs)
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kernel/arch/sparc64/include/mm/sun4u/tlb.h
rc40e6ef rbd48f4c 100 100 #include <arch/barrier.h> 101 101 #include <typedefs.h> 102 #include <trace.h> 102 103 #include <arch/register.h> 103 104 #include <arch/cpu.h> … … 242 243 * Determine the number of entries in the DMMU's small TLB. 243 244 */ 244 static inline uint16_t tlb_dsmall_size(void)245 NO_TRACE static inline uint16_t tlb_dsmall_size(void) 245 246 { 246 247 return 16; … … 250 251 * Determine the number of entries in each DMMU's big TLB. 251 252 */ 252 static inline uint16_t tlb_dbig_size(void)253 NO_TRACE static inline uint16_t tlb_dbig_size(void) 253 254 { 254 255 return 512; … … 258 259 * Determine the number of entries in the IMMU's small TLB. 259 260 */ 260 static inline uint16_t tlb_ismall_size(void)261 NO_TRACE static inline uint16_t tlb_ismall_size(void) 261 262 { 262 263 return 16; … … 266 267 * Determine the number of entries in the IMMU's big TLB. 267 268 */ 268 static inline uint16_t tlb_ibig_size(void)269 NO_TRACE static inline uint16_t tlb_ibig_size(void) 269 270 { 270 271 if (((ver_reg_t) ver_read()).impl == IMPL_ULTRASPARCIV_PLUS) … … 280 281 * @return Current value of Primary Context Register. 281 282 */ 282 static inline uint64_t mmu_primary_context_read(void)283 NO_TRACE static inline uint64_t mmu_primary_context_read(void) 283 284 { 284 285 return asi_u64_read(ASI_DMMU, VA_PRIMARY_CONTEXT_REG); … … 289 290 * @param v New value of Primary Context Register. 290 291 */ 291 static inline void mmu_primary_context_write(uint64_t v)292 NO_TRACE static inline void mmu_primary_context_write(uint64_t v) 292 293 { 293 294 asi_u64_write(ASI_DMMU, VA_PRIMARY_CONTEXT_REG, v); … … 299 300 * @return Current value of Secondary Context Register. 300 301 */ 301 static inline uint64_t mmu_secondary_context_read(void)302 NO_TRACE static inline uint64_t mmu_secondary_context_read(void) 302 303 { 303 304 return asi_u64_read(ASI_DMMU, VA_SECONDARY_CONTEXT_REG); … … 308 309 * @param v New value of Primary Context Register. 309 310 */ 310 static inline void mmu_secondary_context_write(uint64_t v)311 NO_TRACE static inline void mmu_secondary_context_write(uint64_t v) 311 312 { 312 313 asi_u64_write(ASI_DMMU, VA_SECONDARY_CONTEXT_REG, v); … … 323 324 * Register. 324 325 */ 325 static inline uint64_t itlb_data_access_read(size_t entry)326 NO_TRACE static inline uint64_t itlb_data_access_read(size_t entry) 326 327 { 327 328 itlb_data_access_addr_t reg; … … 337 338 * @param value Value to be written. 338 339 */ 339 static inline void itlb_data_access_write(size_t entry, uint64_t value)340 NO_TRACE static inline void itlb_data_access_write(size_t entry, uint64_t value) 340 341 { 341 342 itlb_data_access_addr_t reg; … … 354 355 * Register. 355 356 */ 356 static inline uint64_t dtlb_data_access_read(size_t entry)357 NO_TRACE static inline uint64_t dtlb_data_access_read(size_t entry) 357 358 { 358 359 dtlb_data_access_addr_t reg; … … 368 369 * @param value Value to be written. 369 370 */ 370 static inline void dtlb_data_access_write(size_t entry, uint64_t value)371 NO_TRACE static inline void dtlb_data_access_write(size_t entry, uint64_t value) 371 372 { 372 373 dtlb_data_access_addr_t reg; … … 384 385 * @return Current value of specified IMMU TLB Tag Read Register. 385 386 */ 386 static inline uint64_t itlb_tag_read_read(size_t entry)387 NO_TRACE static inline uint64_t itlb_tag_read_read(size_t entry) 387 388 { 388 389 itlb_tag_read_addr_t tag; … … 399 400 * @return Current value of specified DMMU TLB Tag Read Register. 400 401 */ 401 static inline uint64_t dtlb_tag_read_read(size_t entry)402 NO_TRACE static inline uint64_t dtlb_tag_read_read(size_t entry) 402 403 { 403 404 dtlb_tag_read_addr_t tag; … … 419 420 * Register. 420 421 */ 421 static inline uint64_t itlb_data_access_read(int tlb, size_t entry)422 NO_TRACE static inline uint64_t itlb_data_access_read(int tlb, size_t entry) 422 423 { 423 424 itlb_data_access_addr_t reg; … … 434 435 * @param value Value to be written. 435 436 */ 436 static inline void itlb_data_access_write(int tlb, size_t entry,437 NO_TRACE static inline void itlb_data_access_write(int tlb, size_t entry, 437 438 uint64_t value) 438 439 { … … 454 455 * Register. 455 456 */ 456 static inline uint64_t dtlb_data_access_read(int tlb, size_t entry)457 NO_TRACE static inline uint64_t dtlb_data_access_read(int tlb, size_t entry) 457 458 { 458 459 dtlb_data_access_addr_t reg; … … 470 471 * @param value Value to be written. 471 472 */ 472 static inline void dtlb_data_access_write(int tlb, size_t entry,473 NO_TRACE static inline void dtlb_data_access_write(int tlb, size_t entry, 473 474 uint64_t value) 474 475 { … … 489 490 * @return Current value of specified IMMU TLB Tag Read Register. 490 491 */ 491 static inline uint64_t itlb_tag_read_read(int tlb, size_t entry)492 NO_TRACE static inline uint64_t itlb_tag_read_read(int tlb, size_t entry) 492 493 { 493 494 itlb_tag_read_addr_t tag; … … 506 507 * @return Current value of specified DMMU TLB Tag Read Register. 507 508 */ 508 static inline uint64_t dtlb_tag_read_read(int tlb, size_t entry)509 NO_TRACE static inline uint64_t dtlb_tag_read_read(int tlb, size_t entry) 509 510 { 510 511 dtlb_tag_read_addr_t tag; … … 523 524 * @param v Value to be written. 524 525 */ 525 static inline void itlb_tag_access_write(uint64_t v)526 NO_TRACE static inline void itlb_tag_access_write(uint64_t v) 526 527 { 527 528 asi_u64_write(ASI_IMMU, VA_IMMU_TAG_ACCESS, v); … … 533 534 * @return Current value of IMMU TLB Tag Access Register. 534 535 */ 535 static inline uint64_t itlb_tag_access_read(void)536 NO_TRACE static inline uint64_t itlb_tag_access_read(void) 536 537 { 537 538 return asi_u64_read(ASI_IMMU, VA_IMMU_TAG_ACCESS); … … 542 543 * @param v Value to be written. 543 544 */ 544 static inline void dtlb_tag_access_write(uint64_t v)545 NO_TRACE static inline void dtlb_tag_access_write(uint64_t v) 545 546 { 546 547 asi_u64_write(ASI_DMMU, VA_DMMU_TAG_ACCESS, v); … … 552 553 * @return Current value of DMMU TLB Tag Access Register. 553 554 */ 554 static inline uint64_t dtlb_tag_access_read(void)555 NO_TRACE static inline uint64_t dtlb_tag_access_read(void) 555 556 { 556 557 return asi_u64_read(ASI_DMMU, VA_DMMU_TAG_ACCESS); … … 562 563 * @param v Value to be written. 563 564 */ 564 static inline void itlb_data_in_write(uint64_t v)565 NO_TRACE static inline void itlb_data_in_write(uint64_t v) 565 566 { 566 567 asi_u64_write(ASI_ITLB_DATA_IN_REG, 0, v); … … 572 573 * @param v Value to be written. 573 574 */ 574 static inline void dtlb_data_in_write(uint64_t v)575 NO_TRACE static inline void dtlb_data_in_write(uint64_t v) 575 576 { 576 577 asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); … … 582 583 * @return Current content of I-SFSR register. 583 584 */ 584 static inline uint64_t itlb_sfsr_read(void)585 NO_TRACE static inline uint64_t itlb_sfsr_read(void) 585 586 { 586 587 return asi_u64_read(ASI_IMMU, VA_IMMU_SFSR); … … 591 592 * @param v New value of I-SFSR register. 592 593 */ 593 static inline void itlb_sfsr_write(uint64_t v)594 NO_TRACE static inline void itlb_sfsr_write(uint64_t v) 594 595 { 595 596 asi_u64_write(ASI_IMMU, VA_IMMU_SFSR, v); … … 601 602 * @return Current content of D-SFSR register. 602 603 */ 603 static inline uint64_t dtlb_sfsr_read(void)604 NO_TRACE static inline uint64_t dtlb_sfsr_read(void) 604 605 { 605 606 return asi_u64_read(ASI_DMMU, VA_DMMU_SFSR); … … 610 611 * @param v New value of D-SFSR register. 611 612 */ 612 static inline void dtlb_sfsr_write(uint64_t v)613 NO_TRACE static inline void dtlb_sfsr_write(uint64_t v) 613 614 { 614 615 asi_u64_write(ASI_DMMU, VA_DMMU_SFSR, v); … … 620 621 * @return Current content of D-SFAR register. 621 622 */ 622 static inline uint64_t dtlb_sfar_read(void)623 NO_TRACE static inline uint64_t dtlb_sfar_read(void) 623 624 { 624 625 return asi_u64_read(ASI_DMMU, VA_DMMU_SFAR); … … 633 634 * @param page Address which is on the page to be demapped. 634 635 */ 635 static inline void itlb_demap(int type, int context_encoding, uintptr_t page)636 NO_TRACE static inline void itlb_demap(int type, int context_encoding, uintptr_t page) 636 637 { 637 638 tlb_demap_addr_t da; … … 659 660 * @param page Address which is on the page to be demapped. 660 661 */ 661 static inline void dtlb_demap(int type, int context_encoding, uintptr_t page)662 NO_TRACE static inline void dtlb_demap(int type, int context_encoding, uintptr_t page) 662 663 { 663 664 tlb_demap_addr_t da;
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