Changeset b3f8fb7 in mainline for kernel/arch/sparc64/include/mm/tsb.h
- Timestamp:
- 2007-01-28T13:25:49Z (17 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 8e8c1a5
- Parents:
- 1ba41c5
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/sparc64/include/mm/tsb.h
r1ba41c5 rb3f8fb7 55 55 #include <arch/mm/mmu.h> 56 56 #include <arch/types.h> 57 #include <typedefs.h> 58 59 /** TSB Tag Target register. */ 60 union tsb_tag_target { 61 uint64_t value; 62 struct { 63 unsigned invalid : 1; /**< Invalidated by software. */ 64 unsigned : 2; 65 unsigned context : 13; /**< Software ASID. */ 66 unsigned : 6; 67 uint64_t va_tag : 42; /**< Virtual address bits <63:22>. */ 68 } __attribute__ ((packed)); 69 }; 70 typedef union tsb_tag_target tsb_tag_target_t; 71 72 /** TSB entry. */ 73 struct tsb_entry { 74 tsb_tag_target_t tag; 75 tte_data_t data; 76 } __attribute__ ((packed)); 77 typedef struct tsb_entry tsb_entry_t; 57 #include <mm/as.h> 78 58 79 59 /** TSB Base register. */ 80 union tsb_base_reg {60 typedef union tsb_base_reg { 81 61 uint64_t value; 82 62 struct { … … 91 71 * 512 * 2^size. */ 92 72 } __attribute__ ((packed)); 93 }; 94 typedef union tsb_base_reg tsb_base_reg_t; 73 } tsb_base_reg_t; 95 74 96 75 /** Read ITSB Base register.
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