Changeset aa85487 in mainline for kernel/arch/sparc64/include/atomic.h
 Timestamp:
 20100307T15:11:56Z (14 years ago)
 Branches:
 lfn, master, serial, ticket/834toolchainupdate, topic/msimupgrade
 Children:
 aadf01e
 Parents:
 2e99277 (diff), 137691a (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
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kernel/arch/sparc64/include/atomic.h
r2e99277 raa85487 27 27 */ 28 28 29 /** @addtogroup sparc64 29 /** @addtogroup sparc64 30 30 * @{ 31 31 */ … … 45 45 * 46 46 * @param val Atomic variable. 47 * @param i Signed value to be added.47 * @param i Signed value to be added. 48 48 * 49 49 * @return Value of the atomic variable as it existed before addition. 50 * 50 51 */ 51 static inline long atomic_add(atomic_t *val, int i)52 static inline atomic_count_t atomic_add(atomic_t *val, atomic_count_t i) 52 53 { 53 uint64_t a, b; 54 54 atomic_count_t a; 55 atomic_count_t b; 56 55 57 do { 56 volatile uintptr_t x = (uint64_t) &val>count;57 58 a = *(( uint64_t *) x);58 volatile uintptr_t ptr = (uintptr_t) &val>count; 59 60 a = *((atomic_count_t *) ptr); 59 61 b = a + i; 60 asm volatile ("casx %0, %2, %1\n" : "+m" (*((uint64_t *)x)), 61 "+r" (b) : "r" (a)); 62 63 asm volatile ( 64 "casx %0, %2, %1\n" 65 : "+m" (*((atomic_count_t *) ptr)), 66 "+r" (b) 67 : "r" (a) 68 ); 62 69 } while (a != b); 63 70 64 71 return a; 65 72 } 66 73 67 static inline longatomic_preinc(atomic_t *val)74 static inline atomic_count_t atomic_preinc(atomic_t *val) 68 75 { 69 76 return atomic_add(val, 1) + 1; 70 77 } 71 78 72 static inline longatomic_postinc(atomic_t *val)79 static inline atomic_count_t atomic_postinc(atomic_t *val) 73 80 { 74 81 return atomic_add(val, 1); 75 82 } 76 83 77 static inline longatomic_predec(atomic_t *val)84 static inline atomic_count_t atomic_predec(atomic_t *val) 78 85 { 79 86 return atomic_add(val, 1)  1; 80 87 } 81 88 82 static inline longatomic_postdec(atomic_t *val)89 static inline atomic_count_t atomic_postdec(atomic_t *val) 83 90 { 84 91 return atomic_add(val, 1); … … 95 102 } 96 103 97 static inline longtest_and_set(atomic_t *val)104 static inline atomic_count_t test_and_set(atomic_t *val) 98 105 { 99 uint64_t v = 1; 100 volatile uintptr_t x = (uint64_t) &val>count; 101 102 asm volatile ("casx %0, %2, %1\n" : "+m" (*((uint64_t *) x)), 103 "+r" (v) : "r" (0)); 104 106 atomic_count_t v = 1; 107 volatile uintptr_t ptr = (uintptr_t) &val>count; 108 109 asm volatile ( 110 "casx %0, %2, %1\n" 111 : "+m" (*((atomic_count_t *) ptr)), 112 "+r" (v) 113 : "r" (0) 114 ); 115 105 116 return v; 106 117 } … … 108 119 static inline void atomic_lock_arch(atomic_t *val) 109 120 { 110 uint64_t tmp1 = 1;111 uint64_t tmp2 = 0;112 113 volatile uintptr_t x = (uint64_t) &val>count;114 121 atomic_count_t tmp1 = 1; 122 atomic_count_t tmp2 = 0; 123 124 volatile uintptr_t ptr = (uintptr_t) &val>count; 125 115 126 preemption_disable(); 116 127 117 128 asm volatile ( 118 "0:\n" 119 "casx %0, %3, %1\n" 120 "brz %1, 2f\n" 121 "nop\n" 122 "1:\n" 123 "ldx %0, %2\n" 124 "brz %2, 0b\n" 125 "nop\n" 126 "ba %%xcc, 1b\n" 127 "nop\n" 128 "2:\n" 129 : "+m" (*((uint64_t *) x)), "+r" (tmp1), "+r" (tmp2) : "r" (0) 129 "0:\n" 130 "casx %0, %3, %1\n" 131 "brz %1, 2f\n" 132 "nop\n" 133 "1:\n" 134 "ldx %0, %2\n" 135 "brz %2, 0b\n" 136 "nop\n" 137 "ba %%xcc, 1b\n" 138 "nop\n" 139 "2:\n" 140 : "+m" (*((atomic_count_t *) ptr)), 141 "+r" (tmp1), 142 "+r" (tmp2) 143 : "r" (0) 130 144 ); 131 145
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