Changeset a35b458 in mainline for boot/arch/ppc32/src/asm.S
- Timestamp:
- 2018-03-02T20:10:49Z (6 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- f1380b7
- Parents:
- 3061bc1
- git-author:
- Jiří Zárevúcky <zarevucky.jiri@…> (2018-02-28 17:38:31)
- git-committer:
- Jiří Zárevúcky <zarevucky.jiri@…> (2018-03-02 20:10:49)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
boot/arch/ppc32/src/asm.S
r3061bc1 ra35b458 48 48 li \reg, 0 49 49 sync 50 50 51 51 .rept 64 52 52 tlbie \reg 53 53 addi \reg, \reg, 0x1000 54 54 .endr 55 55 56 56 eieio 57 57 tlbsync … … 61 61 .macro BAT_COMPUTE base size mask lower upper 62 62 # less than 128 KB -> no BAT 63 63 64 64 lis \upper, 0x0002 65 65 cmpw \size, \upper 66 66 blt no_bat 67 67 68 68 # mask = total >> 18 69 69 70 70 li \upper, 18 71 71 srw \mask, \size, \upper 72 72 73 73 # create Block Length mask by replicating 74 74 # the leading logical one 14 times 75 75 76 76 li \upper, 14 77 77 mtctr \mask 78 78 li \upper, 1 79 79 80 80 0: 81 81 # mask = (mask >> 1) | mask 82 82 83 83 srw \lower, \mask, \upper 84 84 or \mask, \mask, \lower 85 85 86 86 bdnz 0b 87 87 88 88 # mask = mask & 0x07ff 89 89 # (BAT can map up to 256 MB) 90 90 91 91 andi. \mask, \mask, 0x07ff 92 92 93 93 # mask = (mask << 2) | 0x0002 94 94 # (priviledged access only) 95 95 96 96 li \upper, 2 97 97 slw \mask, \mask, \upper 98 98 ori \mask, \mask, 0x0002 99 99 100 100 lis \upper, (0x8000 + \base) 101 101 or \upper, \upper, \mask 102 102 103 103 lis \lower, \base 104 104 ori \lower, \lower, 0x0002 … … 111 111 addi r4, r4, ofw_cif@l 112 112 stw r5, 0(r4) 113 113 114 114 bl ofw_init 115 115 b bootstrap … … 127 127 # r5 = pages to translate 128 128 # r6 = real mode meeting point (physical address) 129 129 130 130 # disable interrupts 131 131 132 132 mfmsr r31 133 133 rlwinm r31, r31, 0, 17, 15 134 134 mtmsr r31 135 135 136 136 # set real mode meeting point physical address 137 137 138 138 mtspr srr0, r6 139 139 140 140 # jump to real_mode 141 141 142 142 mfmsr r31 143 143 lis r30, ~0@h … … 145 145 and r31, r31, r30 146 146 mtspr srr1, r31 147 147 148 148 sync 149 149 isync … … 155 155 .align PAGE_WIDTH 156 156 SYMBOL(real_mode) 157 157 158 158 # arguments: 159 159 # r3 = bootinfo (physical address) 160 160 # r4 = translate table (physical address) 161 161 # r5 = pages to translate 162 162 163 163 # move the images of components to the proper 164 164 # location using the translate table 165 165 166 166 li r31, PAGE_SIZE >> 2 167 167 li r30, 0 168 168 169 169 page_copy: 170 170 171 171 cmpwi r5, 0 172 172 beq copy_end 173 173 174 174 mtctr r31 175 175 lwz r29, 0(r4) 176 176 177 177 copy_loop: 178 178 179 179 lwz r28, 0(r29) 180 180 stw r28, 0(r30) 181 181 182 182 SMC_COHERENCY r30 183 183 184 184 addi r29, r29, 4 185 185 addi r30, r30, 4 186 186 187 187 bdnz copy_loop 188 188 189 189 addi r4, r4, 4 190 190 subi r5, r5, 1 191 191 b page_copy 192 192 193 193 copy_end: 194 194 195 195 # initially fill segment registers 196 196 197 197 li r31, 0 198 198 199 199 li r29, 8 200 200 mtctr r29 201 201 li r30, 0 # ASID 0 (VSIDs 0 .. 7) 202 202 203 203 seg_fill_uspace: 204 204 205 205 mtsrin r30, r31 206 206 addi r30, r30, 1 207 207 addis r31, r31, 0x1000 # move to next SR 208 208 209 209 bdnz seg_fill_uspace 210 210 211 211 li r29, 8 212 212 mtctr r29 213 213 lis r30, 0x4000 # priviledged access only 214 214 ori r30, r30, 8 # ASID 0 (VSIDs 8 .. 15) 215 215 216 216 seg_fill_kernel: 217 217 218 218 mtsrin r30, r31 219 219 addi r30, r30, 1 220 220 addis r31, r31, 0x1000 # move to next SR 221 221 222 222 bdnz seg_fill_kernel 223 223 224 224 # invalidate block address translation registers 225 225 226 226 li r30, 0 227 227 228 228 mtspr ibat0u, r30 229 229 mtspr ibat0l, r30 230 230 231 231 mtspr ibat1u, r30 232 232 mtspr ibat1l, r30 233 233 234 234 mtspr ibat2u, r30 235 235 mtspr ibat2l, r30 236 236 237 237 mtspr ibat3u, r30 238 238 mtspr ibat3l, r30 239 239 240 240 mtspr dbat0u, r30 241 241 mtspr dbat0l, r30 242 242 243 243 mtspr dbat1u, r30 244 244 mtspr dbat1l, r30 245 245 246 246 mtspr dbat2u, r30 247 247 mtspr dbat2l, r30 248 248 249 249 mtspr dbat3u, r30 250 250 mtspr dbat3l, r30 251 251 252 252 # create empty Page Hash Table 253 253 # on top of memory, size 64 KB 254 254 255 255 lwz r31, 4(r3) # r31 = memory size 256 256 257 257 lis r30, 65536@h 258 258 ori r30, r30, 65536@l # r30 = 65536 259 259 260 260 subi r29, r30, 1 # r29 = 65535 261 261 262 262 sub r31, r31, r30 263 263 andc r31, r31, r29 # pht = ALIGN_DOWN(memory_size - 65536, 65536) 264 264 265 265 mtsdr1 r31 266 266 267 267 li r29, 2 268 268 srw r30, r30, r29 # r30 = 16384 269 269 li r29, 0 270 270 271 271 pht_clear: 272 272 273 273 # write zeroes 274 274 275 275 stw r29, 0(r31) 276 276 FLUSH_DCACHE r31 277 277 278 278 addi r31, r31, 4 279 279 subi r30, r30, 4 280 280 281 281 cmpwi r30, 0 282 282 beq clear_end 283 283 284 284 bdnz pht_clear 285 285 286 286 clear_end: 287 287 288 288 # create BAT identity mapping 289 289 290 290 lwz r31, 4(r3) # r31 = memory size 291 291 292 292 lis r30, 268435456@h 293 293 ori r30, r30, 268435456@l # r30 = 256 MB 294 294 295 295 # BAT0 296 296 297 297 # r29 = min(r31, r30) 298 298 299 299 cmpw r31, r30 300 300 blt bat0_r31 301 301 302 302 mr r29, r30 303 303 b bat0_r30 304 304 305 305 bat0_r31: 306 306 307 307 mr r29, r31 308 308 309 309 bat0_r30: 310 310 311 311 BAT_COMPUTE 0x0000 r29 r28 r27 r26 312 312 mtspr ibat0u, r26 313 313 mtspr ibat0l, r27 314 314 315 315 mtspr dbat0u, r26 316 316 mtspr dbat0l, r27 317 317 318 318 # BAT1 319 319 320 320 sub r31, r31, r29 # r31 = r31 - r29 321 321 322 322 # r29 = min(r31, r30) 323 323 324 324 cmpw r31, r30 325 325 blt bat1_r31 326 326 327 327 mr r29, r30 328 328 b bat1_r30 329 329 330 330 bat1_r31: 331 331 332 332 mr r29, r31 333 333 334 334 bat1_r30: 335 335 336 336 BAT_COMPUTE 0x1000 r29 r28 r27 r26 337 337 mtspr ibat1u, r26 338 338 mtspr ibat1l, r27 339 339 340 340 mtspr dbat1u, r26 341 341 mtspr dbat1l, r27 342 342 343 343 # BAT2 344 344 345 345 sub r31, r31, r29 # r31 = r31 - r29 346 346 347 347 # r29 = min(r31, r30) 348 348 349 349 cmpw r31, r30 350 350 blt bat2_r31 351 351 352 352 mr r29, r30 353 353 b bat2_r30 354 354 355 355 bat2_r31: 356 356 357 357 mr r29, r31 358 358 359 359 bat2_r30: 360 360 361 361 BAT_COMPUTE 0x2000 r29 r28 r27 r26 362 362 mtspr ibat2u, r26 363 363 mtspr ibat2l, r27 364 364 365 365 mtspr dbat2u, r26 366 366 mtspr dbat2l, r27 367 367 368 368 # BAT3 369 369 370 370 sub r31, r31, r29 # r31 = r31 - r29 371 371 372 372 # r29 = min(r31, r30) 373 373 374 374 cmpw r31, r30 375 375 blt bat3_r31 376 376 377 377 mr r29, r30 378 378 b bat3_r30 379 379 380 380 bat3_r31: 381 381 382 382 mr r29, r31 383 383 384 384 bat3_r30: 385 385 386 386 BAT_COMPUTE 0x3000 r29 r28 r27 r26 387 387 mtspr ibat3u, r26 388 388 mtspr ibat3l, r27 389 389 390 390 mtspr dbat3u, r26 391 391 mtspr dbat3l, r27 392 392 393 393 no_bat: 394 394 395 395 # flush TLB 396 396 397 397 TLB_FLUSH r31 398 398 399 399 # start the kernel 400 400 # … … 404 404 # sprg3 = physical memory size 405 405 # sp = 0 (enforces the usage of sprg0 as exception stack) 406 406 407 407 lis r31, PA2KA(BOOT_OFFSET)@ha 408 408 addi r31, r31, PA2KA(BOOT_OFFSET)@l 409 409 mtspr srr0, r31 410 410 411 411 lis r31, BOOT_OFFSET@ha 412 412 addi r31, r31, BOOT_OFFSET@l 413 413 mtsprg0 r31 414 414 415 415 # bootinfo starts with a 64 bit integer containing 416 416 # the physical memory size, get the lower 4 bytes 417 417 418 418 lwz r31, 4(r3) 419 419 mtsprg3 r31 420 420 421 421 li sp, 0 422 422 423 423 mfmsr r31 424 424 ori r31, r31, (msr_ir | msr_dr)@l 425 425 mtspr srr1, r31 426 426 427 427 sync 428 428 isync
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