Changeset a1f60f3 in mainline for kernel/arch/amd64/src/asm_utils.S
- Timestamp:
- 2010-06-27T23:04:20Z (14 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 64f6ef04
- Parents:
- 33dac7d
- File:
-
- 1 edited
-
kernel/arch/amd64/src/asm_utils.S (modified) (14 diffs)
Legend:
- Unmodified
- Added
- Removed
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kernel/arch/amd64/src/asm_utils.S
r33dac7d ra1f60f3 27 27 # 28 28 29 #define IREGISTER_SPACE 80 30 31 #define IOFFSET_RAX 0x0 32 #define IOFFSET_RCX 0x8 33 #define IOFFSET_RDX 0x10 34 #define IOFFSET_RSI 0x18 35 #define IOFFSET_RDI 0x20 36 #define IOFFSET_R8 0x28 37 #define IOFFSET_R9 0x30 38 #define IOFFSET_R10 0x38 39 #define IOFFSET_R11 0x40 40 #define IOFFSET_RBP 0x48 41 42 # Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int has no error word 43 # and 1 means interrupt with error word 44 #define ERROR_WORD_INTERRUPT_LIST 0x00027D00 29 #define IREGISTER_SPACE 80 30 31 #define IOFFSET_RAX 0x00 32 #define IOFFSET_RCX 0x08 33 #define IOFFSET_RDX 0x10 34 #define IOFFSET_RSI 0x18 35 #define IOFFSET_RDI 0x20 36 #define IOFFSET_R8 0x28 37 #define IOFFSET_R9 0x30 38 #define IOFFSET_R10 0x38 39 #define IOFFSET_R11 0x40 40 #define IOFFSET_RBP 0x48 41 42 # Mask for interrupts 0 - 31 (bits 0 - 31) where 0 means that int 43 # has no error word and 1 means interrupt with error word 44 45 #define ERROR_WORD_INTERRUPT_LIST 0x00027D00 45 46 46 47 #include <arch/pm.h> 47 48 #include <arch/mm/page.h> 48 49 49 50 .text 50 51 .global interrupt_handlers … … 53 54 54 55 panic_printf: 55 movq $halt, (%rsp) 56 movabsq $halt, %rax 57 movq %rax, (%rsp) 56 58 jmp printf 57 59 … … 76 78 jmp _memsetw 77 79 78 #define MEMCPY_DST 79 #define MEMCPY_SRC 80 #define MEMCPY_SIZE 80 #define MEMCPY_DST %rdi 81 #define MEMCPY_SRC %rsi 82 #define MEMCPY_SIZE %rdx 81 83 82 84 /** … … 89 91 * or copy_to_uspace(). 90 92 * 91 * @param MEMCPY_DST 92 * @param MEMCPY_SRC 93 * @param MEMCPY_SIZE 93 * @param MEMCPY_DST Destination address. 94 * @param MEMCPY_SRC Source address. 95 * @param MEMCPY_SIZE Number of bytes to copy. 94 96 * 95 97 * @retrun MEMCPY_DST on success, 0 on failure. 98 * 96 99 */ 97 100 memcpy: … … 99 102 memcpy_to_uspace: 100 103 movq MEMCPY_DST, %rax 101 104 102 105 movq MEMCPY_SIZE, %rcx 103 shrq $3, %rcx 104 105 rep movsq 106 106 shrq $3, %rcx /* size / 8 */ 107 108 rep movsq /* copy as much as possible word by word */ 109 107 110 movq MEMCPY_SIZE, %rcx 108 andq $7, %rcx 111 andq $7, %rcx /* size % 8 */ 109 112 jz 0f 110 113 111 rep movsb 112 113 0:114 ret/* return MEMCPY_SRC, success */114 rep movsb /* copy the rest byte by byte */ 115 116 0: 117 ret /* return MEMCPY_SRC, success */ 115 118 116 119 memcpy_from_uspace_failover_address: 117 120 memcpy_to_uspace_failover_address: 118 xorq %rax, %rax 121 xorq %rax, %rax /* return 0, failure */ 119 122 ret 120 123 … … 124 127 # 125 128 has_cpuid: 126 pushfq 127 popq %rax 128 movq %rax, %rdx# copy flags129 btcl $21, %edx# swap the ID bit129 pushfq # store flags 130 popq %rax # read flags 131 movq %rax, %rdx # copy flags 132 btcl $21, %edx # swap the ID bit 130 133 pushq %rdx 131 popfq 134 popfq # propagate the change into flags 132 135 pushfq 133 popq %rdx # read flags134 andl $(1 <<21),%eax# interested only in ID bit135 andl $(1 <<21),%edx136 xorl %edx, %eax# 0 if not supported, 1 if supported136 popq %rdx # read flags 137 andl $(1 << 21), %eax # interested only in ID bit 138 andl $(1 << 21), %edx 139 xorl %edx, %eax # 0 if not supported, 1 if supported 137 140 ret 138 141 139 142 cpuid: 140 movq %rbx, %r10 # we have to preserve rbx across function calls141 142 movl %edi,%eax 143 144 cpuid 145 movl %eax, 0(%rsi)146 movl %ebx, 4(%rsi)147 movl %ecx, 8(%rsi)148 movl %edx, 12(%rsi)149 143 movq %rbx, %r10 # we have to preserve rbx across function calls 144 145 movl %edi,%eax # load the command into %eax 146 147 cpuid 148 movl %eax, 0(%rsi) 149 movl %ebx, 4(%rsi) 150 movl %ecx, 8(%rsi) 151 movl %edx, 12(%rsi) 152 150 153 movq %r10, %rbx 151 154 ret … … 157 160 wrmsr 158 161 ret 159 162 160 163 read_efer_flag: 161 164 movq $0xc0000080, %rcx 162 165 rdmsr 163 ret 166 ret 164 167 165 168 # Push all volatile general purpose registers on stack … … 190 193 .endm 191 194 192 #define INTERRUPT_ALIGN 128193 195 #define INTERRUPT_ALIGN 128 196 194 197 ## Declare interrupt handlers 195 198 # … … 200 203 # 201 204 .macro handler i n 202 205 203 206 /* 204 207 * Choose between version with error code and version without error … … 209 212 * Therefore we align the interrupt handlers. 210 213 */ 211 214 212 215 .iflt \i-32 213 216 .if (1 << \i) & ERROR_WORD_INTERRUPT_LIST … … 220 223 * Version without error word, 221 224 */ 222 subq $(IREGISTER_SPACE +8), %rsp225 subq $(IREGISTER_SPACE + 8), %rsp 223 226 .endif 224 227 .else … … 226 229 * Version without error word, 227 230 */ 228 subq $(IREGISTER_SPACE +8), %rsp229 .endif 230 231 subq $(IREGISTER_SPACE + 8), %rsp 232 .endif 233 231 234 save_all_gpr 232 235 cld 233 236 234 237 # Stop stack traces here 235 238 xorq %rbp, %rbp 236 237 movq $(\i), %rdi 238 movq %rsp, %rsi 239 call exc_dispatch 239 240 movq $(\i), %rdi # %rdi - first parameter 241 movq %rsp, %rsi # %rsi - pointer to istate 242 call exc_dispatch # exc_dispatch(i, istate) 240 243 241 244 restore_all_gpr 242 245 # $8 = Skip error word 243 addq $(IREGISTER_SPACE +8), %rsp246 addq $(IREGISTER_SPACE + 8), %rsp 244 247 iretq 245 248 246 249 .align INTERRUPT_ALIGN 247 .if (\n -\i)-1248 handler "(\i+1)",\n250 .if (\n - \i) - 1 251 handler "(\i + 1)", \n 249 252 .endif 250 253 .endm … … 252 255 .align INTERRUPT_ALIGN 253 256 interrupt_handlers: 254 h_start:255 handler 0 IDT_ITEMS256 h_end:257 h_start: 258 handler 0 IDT_ITEMS 259 h_end: 257 260 258 261 ## Low-level syscall handler 259 # 262 # 260 263 # Registers on entry: 261 264 # 262 # @param rcx 263 # @param r11 264 # 265 # @param rax 266 # @param rdi 267 # @param rsi 268 # @param rdx 269 # @param r10 4th syscall argument. Used instead of RCX because the270 # 271 # @param r8 272 # @param r9 273 # 274 # @return 265 # @param rcx Userspace return address. 266 # @param r11 Userspace RLFAGS. 267 # 268 # @param rax Syscall number. 269 # @param rdi 1st syscall argument. 270 # @param rsi 2nd syscall argument. 271 # @param rdx 3rd syscall argument. 272 # @param r10 4th syscall argument. Used instead of RCX because 273 # the SYSCALL instruction clobbers it. 274 # @param r8 5th syscall argument. 275 # @param r9 6th syscall argument. 276 # 277 # @return Return value is in rax. 275 278 # 276 279 syscall_entry: 277 swapgs # Switch to hidden gs 278 # 279 # %gs:0 Scratch space for this thread's user RSP 280 # %gs:8 Address to be used as this thread's kernel RSP 280 swapgs # Switch to hidden gs 281 281 # 282 movq %rsp, %gs:0 # Save this thread's user RSP 283 movq %gs:8, %rsp # Set this thread's kernel RSP 284 swapgs # Switch back to remain consistent 282 # %gs:0 Scratch space for this thread's user RSP 283 # %gs:8 Address to be used as this thread's kernel RSP 284 # 285 movq %rsp, %gs:0 # Save this thread's user RSP 286 movq %gs:8, %rsp # Set this thread's kernel RSP 287 swapgs # Switch back to remain consistent 285 288 sti 286 289 287 290 pushq %rcx 288 291 pushq %r11 289 290 movq %r10, %rcx 292 293 movq %r10, %rcx # Copy the 4th argument where it is expected 291 294 pushq %rax 292 295 call syscall_handler 293 296 addq $8, %rsp 294 297 295 298 popq %r11 296 299 popq %rcx 297 300 298 301 cli 299 302 swapgs 300 movq %gs:0, %rsp 303 movq %gs:0, %rsp # Restore the user RSP 301 304 swapgs 302 305 303 306 sysretq 304 307 … … 306 309 .global interrupt_handler_size 307 310 308 interrupt_handler_size: .quad (h_end -h_start)/IDT_ITEMS311 interrupt_handler_size: .quad (h_end - h_start) / IDT_ITEMS
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