Changeset a1d636e in mainline for boot/arch/arm32/src/mm.c

Timestamp:

2015-09-17T07:19:30Z (9 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

f834cc32

Parents:

5f310ec8

Message:

Access CP15 register 2 wrt. target architecture and implementation

CP15 register 2 controls the Translation Table Base and Translation
Table Base Control registers.

• Do not define macros for functionality which is not supported by the target architecture or implementation.
• ARMv4 and ARMv5 define bits 13:0 as unpredictable/should be zero.

File:

• boot/arch/arm32/src/mm.c (modified) (1 diff)

boot/arch/arm32/src/mm.c

@@ -189 +189 @@
          */
         uint32_t val = (uint32_t)boot_pt & TTBR_ADDR_MASK;
+#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
+        // FIXME: TTBR_RGN_WBWA_CACHE is unpredictable on ARMv6
         val |= TTBR_RGN_WBWA_CACHE | TTBR_C_FLAG;
+#endif
         TTBR0_write(val);
 }