Changeset 9f491d7 in mainline

Timestamp:

2008-06-16T21:42:48Z (16 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

4a23cb6

Parents:

ad2e39b

Message:

First argument of atomic functions is read-write (ia32).

Files:

• kernel/arch/ia32/include/atomic.h (modified) (7 diffs)
• uspace/lib/libc/arch/ia32/include/atomic.h (modified) (4 diffs)

kernel/arch/ia32/include/atomic.h

@@ -42 +42 @@
 static inline void atomic_inc(atomic_t *val) {
 #ifdef CONFIG_SMP
-        asm volatile ("lock incl %0\n" : "=m" (val->count));
+        asm volatile ("lock incl %0\n" : "+m" (val->count));
 #else
-        asm volatile ("incl %0\n" : "=m" (val->count));
+        asm volatile ("incl %0\n" : "+m" (val->count));
 #endif /* CONFIG_SMP */
 }
@@ -50 +50 @@
 static inline void atomic_dec(atomic_t *val) {
 #ifdef CONFIG_SMP
-        asm volatile ("lock decl %0\n" : "=m" (val->count));
+        asm volatile ("lock decl %0\n" : "+m" (val->count));
 #else
-        asm volatile ("decl %0\n" : "=m" (val->count));
+        asm volatile ("decl %0\n" : "+m" (val->count));
 #endif /* CONFIG_SMP */
 }
@@ -62 +62 @@
         asm volatile (
                 "lock xaddl %1, %0\n"
-                : "=m" (val->count), "+r" (r)
+                : "+m" (val->count), "+r" (r)
         );
 
@@ -74 +74 @@
         asm volatile (
                 "lock xaddl %1, %0\n"
-                : "=m" (val->count), "+r"(r)
+                : "+m" (val->count), "+r"(r)
         );
         
@@ -80 +80 @@
 }
 
-#define atomic_preinc(val) (atomic_postinc(val)+1)
-#define atomic_predec(val) (atomic_postdec(val)-1)
+#define atomic_preinc(val) (atomic_postinc(val) + 1)
+#define atomic_predec(val) (atomic_postdec(val) - 1)
 
 static inline uint32_t test_and_set(atomic_t *val) {
@@ -89 +89 @@
                 "movl $1, %0\n"
                 "xchgl %0, %1\n"
-                : "=r" (v),"=m" (val->count)
+                : "=r" (v),"+m" (val->count)
         );
         
@@ -102 +102 @@
         preemption_disable();
         asm volatile (
-                "0:;"
+                "0:\n"
 #ifdef CONFIG_HT
-                "pause;" /* Pentium 4's HT love this instruction */
+                "pause\n" /* Pentium 4's HT love this instruction */
 #endif
-                "mov %0, %1;"
-                "testl %1, %1;"
-                "jnz 0b;"       /* Lightweight looping on locked spinlock */
+                "mov %0, %1\n"
+                "testl %1, %1\n"
+                "jnz 0b\n"       /* lightweight looping on locked spinlock */
                 
-                "incl %1;"      /* now use the atomic operation */
-                "xchgl %0, %1;"
-                "testl %1, %1;"
-                "jnz 0b;"
-                : "=m"(val->count),"=r"(tmp)
-                );
+                "incl %1\n"      /* now use the atomic operation */
+                "xchgl %0, %1\n"        
+                "testl %1, %1\n"
+                "jnz 0b\n"
+                : "+m" (val->count), "=r"(tmp)
+        );
         /*
          * Prevent critical section code from bleeding out this way up.

uspace/lib/libc/arch/ia32/include/atomic.h

@@ -37 +37 @@
 
 static inline void atomic_inc(atomic_t *val) {
-        asm volatile ("lock incl %0\n" : "=m" (val->count));
+        asm volatile ("lock incl %0\n" : "+m" (val->count));
 }
 
 static inline void atomic_dec(atomic_t *val) {
-        asm volatile ("lock decl %0\n" : "=m" (val->count));
+        asm volatile ("lock decl %0\n" : "+m" (val->count));
 }
 
@@ -51 +51 @@
                 "movl $1, %0\n"
                 "lock xaddl %0, %1\n"
-                : "=r" (r), "=m" (val->count)
+                : "=r" (r), "+m" (val->count)
         );
 
@@ -64 +64 @@
                 "movl $-1, %0\n"
                 "lock xaddl %0, %1\n"
-                : "=r" (r), "=m" (val->count)
+                : "=r" (r), "+m" (val->count)
         );
         
@@ -70 +70 @@
 }
 
-#define atomic_preinc(val) (atomic_postinc(val)+1)
-#define atomic_predec(val) (atomic_postdec(val)-1)
+#define atomic_preinc(val) (atomic_postinc(val) + 1)
+#define atomic_predec(val) (atomic_postdec(val) - 1)
 
 #endif