Changeset 9cc0d7c in mainline

Timestamp:

2007-11-17T14:12:48Z (16 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

7e956eb

Parents:

05ae7081

Message:

Support for six syscall arguments for arm32.

Files:

• kernel/arch/arm32/src/exception.c (modified) (2 diffs)
• uspace/lib/libc/arch/arm32/src/syscall.c (modified) (2 diffs)

kernel/arch/arm32/src/exception.c

@@ -215 +215 @@
          * where handler's address is stored
         */
-        volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE - PREFETCH_OFFSET;
+        volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE -
+            PREFETCH_OFFSET;
         
         /* make it LDR instruction and store at exception vector */
@@ -287 +288 @@
 static void swi_exception(int exc_no, istate_t *istate)
 {
-        /*
-        dprintf("SYSCALL: r0-r4: %x, %x, %x, %x, %x; pc: %x\n", istate->r0, 
-                istate->r1, istate->r2, istate->r3, istate->r4, istate->pc);
-        */
-
         istate->r0 = syscall_handler(istate->r0, istate->r1, istate->r2,
-            istate->r3, istate->r4);
+            istate->r3, istate->r4, istate->r5, istate->r6);
 }
 

uspace/lib/libc/arch/arm32/src/syscall.c

@@ -51 +51 @@
  */
 sysarg_t __syscall(const sysarg_t p1, const sysarg_t p2, const sysarg_t p3,
-    const sysarg_t p4, const syscall_t id)
+    const sysarg_t p4, const sysarg_t p5, const sysarg_t p6, const syscall_t id)
 {
         register sysarg_t __arm_reg_r0 asm("r0") = p1;
@@ -57 +57 @@
         register sysarg_t __arm_reg_r2 asm("r2") = p3;
         register sysarg_t __arm_reg_r3 asm("r3") = p4;
-        register sysarg_t __arm_reg_r4 asm("r4") = id;
+        register sysarg_t __arm_reg_r4 asm("r4") = p5;
+        register sysarg_t __arm_reg_r5 asm("r5") = p6;
+        register sysarg_t __arm_reg_r6 asm("r6") = id;
 
         asm volatile ( "swi"
                 : "=r" (__arm_reg_r0)
-                : "r"  (__arm_reg_r0),
-                  "r"  (__arm_reg_r1),
-                  "r"  (__arm_reg_r2),
-                  "r"  (__arm_reg_r3),
-                  "r"  (__arm_reg_r4)
+                : "r" (__arm_reg_r0),
+                  "r" (__arm_reg_r1),
+                  "r" (__arm_reg_r2),
+                  "r" (__arm_reg_r3),
+                  "r" (__arm_reg_r4),
+                  "r" (__arm_reg_r5),
+                  "r" (__arm_reg_r6)
         );