Changeset 965dc18 in mainline for boot/arch/sparc64/loader/asm.S
- Timestamp:
- 2008-12-05T19:59:03Z (15 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 49093a4
- Parents:
- 0258e67
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
boot/arch/sparc64/loader/asm.S
r0258e67 r965dc18 106 106 * 2. Invalidate I-cache. 107 107 * 3. Flush instruction pipeline. 108 */ 109 call icache_flush 110 membar #StoreStore 108 */ 109 110 /* 111 * US3 processors have a write-invalidate cache, so explicitly 112 * invalidating it is not required. Whether to invalidate I-cache 113 * or not is decided according to the value of the global 114 * "subarchitecture" variable (set in the bootstrap). 115 */ 116 set subarchitecture, %g2 117 ldub [%g2], %g2 118 cmp %g2, 3 119 be 1f 120 nop 121 0: 122 call icache_flush 123 nop 124 1: 125 membar #StoreStore 126 127 /* 128 * Flush the instruction pipeline. 129 */ 111 130 flush %i7 112 131 … … 135 154 ! SF Erratum #51 136 155 nop 137 138 156 .global ofw 139 157 ofw:
Note:
See TracChangeset
for help on using the changeset viewer.