Fork us on GitHub Follow us on Facebook Follow us on Twitter

Changeset 93d8022 in mainline


Ignore:
Timestamp:
2015-10-26T21:12:57Z (5 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
master
Children:
5783d10
Parents:
1a2a6e7
Message:

ARM cache handling fixes

  • boot: Use the normal outer and inner WBWA attribute also for ARMv6
  • kernel: Fix comment in page_armv6.h:set_pt_level0_flags(). TEX=5, C=0, B=1 encodes outer and inner WBWA normal memory.
  • Treat all normal memory as non shareable also on ARMv6.
  • Make sure D$ is invalidated in cpu_arch_init() before it is enabled.
  • For non-cacheable ARMv6+ memory, use device memory type instead of strongly-ordered.
  • For ARMv5-, use either cached/buffered (CB=0b11) or uncached/unbuffered (CB=0b00).
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • boot/arch/arm32/src/mm.c

    r1a2a6e7 r93d8022  
    143143        pte->should_be_zero_1 = 0;
    144144        pte->access_permission_0 = PTE_AP_USER_NO_KERNEL_RW;
    145 #ifdef PROCESSOR_ARCH_armv7_a
     145#if defined(PROCESSOR_ARCH_armv6) || defined(PROCESSOR_ARCH_armv7_a)
    146146        /*
    147147         * Keeps this setting in sync with memory type attributes in:
     
    152152        pte->tex = section_cacheable(frame) ? 5 : 0;
    153153        pte->cacheable = section_cacheable(frame) ? 0 : 0;
    154         pte->bufferable = section_cacheable(frame) ? 1 : 0;
     154        pte->bufferable = section_cacheable(frame) ? 1 : 1;
    155155#else
    156         pte->bufferable = 1;
     156        pte->bufferable = section_cacheable(frame);
    157157        pte->cacheable = section_cacheable(frame);
    158158        pte->tex = 0;
  • kernel/arch/arm32/include/arch/cache.h

    r1a2a6e7 r93d8022  
    4646void cpu_dcache_flush_invalidate(void);
    4747extern void icache_invalidate(void);
     48extern void dcache_invalidate(void);
    4849extern void dcache_clean_mva_pou(uintptr_t);
    4950
  • kernel/arch/arm32/include/arch/mm/page_armv6.h

    r1a2a6e7 r93d8022  
    257257        if (flags & PAGE_CACHEABLE) {
    258258                /*
    259                  * Write-through, write-allocate memory, see ch. B3.8.2
    260                  * (p. B3-1358) of ARM Architecture reference manual.
     259                 * Outer and inner write-back, write-allocate memory,
     260                 * see ch. B3.8.2 (p. B3-1358) of ARM Architecture reference
     261                 * manual.
     262                 *
    261263                 * Make sure the memory type is correct, and in sync with:
    262264                 * init_boot_pt (boot/arch/arm32/src/mm.c)
     
    277279        }
    278280       
    279 #if defined(PROCESSOR_ARCH_armv6)
    280         /* FIXME: this disables caches */
    281         p->shareable = 1;
    282 #else
    283281        /* Shareable is ignored for devices (non-cacheable),
    284282         * turn it off for normal memory. */
    285283        p->shareable = 0;
    286 #endif
    287284       
    288285        p->non_global = !(flags & PAGE_GLOBAL);
  • kernel/arch/arm32/src/cpu/cpu.c

    r1a2a6e7 r93d8022  
    130130{
    131131        uint32_t control_reg = SCTLR_read();
    132        
     132
     133        dcache_invalidate();
     134        read_barrier();
     135
    133136        /* Turn off tex remap, RAZ/WI prior to armv7 */
    134137        control_reg &= ~SCTLR_TEX_REMAP_EN_FLAG;
     
    341344#endif
    342345
     346void dcache_invalidate(void)
     347{
     348#if defined(PROCESSOR_ARCH_armv7_a)
     349        dcache_flush_invalidate();
     350#else
     351        if (cache_is_unified())
     352                CIALL_write(0);
     353        else
     354                DCIALL_write(0);
     355#endif
     356}
     357
    343358void dcache_clean_mva_pou(uintptr_t mva)
    344359{
Note: See TracChangeset for help on using the changeset viewer.