Changeset 93d8022 in mainline for kernel/arch/arm32/include/arch/mm/page_armv6.h

Timestamp:

2015-10-26T21:12:57Z (8 years ago)

Author:

Jakub Jermar <jakub@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

5783d10

Parents:

1a2a6e7

Message:

ARM cache handling fixes

• boot: Use the normal outer and inner WBWA attribute also for ARMv6
• kernel: Fix comment in page_armv6.h:set_pt_level0_flags(). TEX=5, C=0, B=1 encodes outer and inner WBWA normal memory.
• Treat all normal memory as non shareable also on ARMv6.
• Make sure D$ is invalidated in cpu_arch_init() before it is enabled.
• For non-cacheable ARMv6+ memory, use device memory type instead of strongly-ordered.
• For ARMv5-, use either cached/buffered (CB=0b11) or uncached/unbuffered (CB=0b00).

File:

• kernel/arch/arm32/include/arch/mm/page_armv6.h (modified) (2 diffs)

kernel/arch/arm32/include/arch/mm/page_armv6.h

@@ -257 +257 @@
         if (flags & PAGE_CACHEABLE) {
                 /*
-                 * Write-through, write-allocate memory, see ch. B3.8.2
-                 * (p. B3-1358) of ARM Architecture reference manual.
+                 * Outer and inner write-back, write-allocate memory,
+                 * see ch. B3.8.2 (p. B3-1358) of ARM Architecture reference
+                 * manual.
+                 *
                  * Make sure the memory type is correct, and in sync with:
                  * init_boot_pt (boot/arch/arm32/src/mm.c)
@@ -277 +279 @@
         }
         
-#if defined(PROCESSOR_ARCH_armv6)
-        /* FIXME: this disables caches */
-        p->shareable = 1;
-#else
         /* Shareable is ignored for devices (non-cacheable),
          * turn it off for normal memory. */
         p->shareable = 0;
-#endif
         
         p->non_global = !(flags & PAGE_GLOBAL);