Changeset 8df5f20 in mainline for kernel/arch/sparc64/include/arch/barrier.h
- Timestamp:
- 2019-02-11T14:56:26Z (5 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 4805495
- Parents:
- 391996b
- git-author:
- Jiří Zárevúcky <zarevucky.jiri@…> (2019-02-01 23:26:21)
- git-committer:
- Jiří Zárevúcky <zarevucky.jiri@…> (2019-02-11 14:56:26)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/sparc64/include/arch/barrier.h
r391996b r8df5f20 39 39 40 40 /** Flush Instruction pipeline. */ 41 NO_TRACE static inline void flush_pipeline(void)41 _NO_TRACE static inline void flush_pipeline(void) 42 42 { 43 43 unsigned long pc; … … 62 62 63 63 /** Memory Barrier instruction. */ 64 NO_TRACE static inline void membar(void)64 _NO_TRACE static inline void membar(void) 65 65 { 66 66 asm volatile (
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