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Changeset 84439d7 in mainline for kernel/arch/ia32/include/mm/page.h


Ignore:
Timestamp:
2010-12-05T09:34:46Z (11 years ago)
Author:
Vojtech Horky <vojtechhorky@…>
Branches:
lfn, master
Children:
75732da
Parents:
56b962d (diff), 35537a7 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge with development/

File:
1 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/ia32/include/mm/page.h

    r56b962d r84439d7  
    3939#include <trace.h>
    4040
    41 #define PAGE_WIDTH      FRAME_WIDTH
    42 #define PAGE_SIZE       FRAME_SIZE
     41#define PAGE_WIDTH  FRAME_WIDTH
     42#define PAGE_SIZE   FRAME_SIZE
    4343
    4444#ifdef KERNEL
    4545
    4646#ifndef __ASM__
    47 #       define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
    48 #       define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)
    49 #else
    50 #       define KA2PA(x) ((x) - 0x80000000)
    51 #       define PA2KA(x) ((x) + 0x80000000)
    52 #endif
     47
     48#define KA2PA(x)  (((uintptr_t) (x)) - UINT32_C(0x80000000))
     49#define PA2KA(x)  (((uintptr_t) (x)) + UINT32_C(0x80000000))
     50
     51#else /* __ASM__ */
     52
     53#define KA2PA(x)  ((x) - 0x80000000)
     54#define PA2KA(x)  ((x) + 0x80000000)
     55
     56#endif /* __ASM__ */
    5357
    5458/*
     
    5862
    5963/* Number of entries in each level. */
    60 #define PTL0_ENTRIES_ARCH       1024
    61 #define PTL1_ENTRIES_ARCH       0
    62 #define PTL2_ENTRIES_ARCH       0
    63 #define PTL3_ENTRIES_ARCH       1024
     64#define PTL0_ENTRIES_ARCH  1024
     65#define PTL1_ENTRIES_ARCH  0
     66#define PTL2_ENTRIES_ARCH  0
     67#define PTL3_ENTRIES_ARCH  1024
    6468
    6569/* Page table sizes for each level. */
    66 #define PTL0_SIZE_ARCH          ONE_FRAME
    67 #define PTL1_SIZE_ARCH          0
    68 #define PTL2_SIZE_ARCH          0
    69 #define PTL3_SIZE_ARCH          ONE_FRAME
     70#define PTL0_SIZE_ARCH  ONE_FRAME
     71#define PTL1_SIZE_ARCH  0
     72#define PTL2_SIZE_ARCH  0
     73#define PTL3_SIZE_ARCH  ONE_FRAME
    7074
    7175/* Macros calculating indices for each level. */
    72 #define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 22) & 0x3ff)
    73 #define PTL1_INDEX_ARCH(vaddr)  0
    74 #define PTL2_INDEX_ARCH(vaddr)  0
    75 #define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x3ff)
     76#define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 22) & 0x3ffU)
     77#define PTL1_INDEX_ARCH(vaddr)  0
     78#define PTL2_INDEX_ARCH(vaddr)  0
     79#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x3ffU)
    7680
    7781/* Get PTE address accessors for each level. */
     
    122126#define PTE_WRITABLE_ARCH(p) \
    123127        ((p)->writeable != 0)
    124 #define PTE_EXECUTABLE_ARCH(p)                  1
     128#define PTE_EXECUTABLE_ARCH(p)  1
    125129
    126130#ifndef __ASM__
     
    144148
    145149/** When bit on this position is 1, a reserved bit was set in page directory. */
    146 #define PFERR_CODE_RSVD         (1 << 3)       
     150#define PFERR_CODE_RSVD         (1 << 3)
    147151
    148152/** Page Table Entry. */
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