Changeset 7c3fb9b in mainline for kernel/arch/amd64/src/fpu_context.c

Timestamp:

2018-05-17T08:29:01Z (6 years ago)

Author:

Jiri Svoboda <jiri@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

6ff23ff

Parents:

fac0ac7

git-author:

Jiri Svoboda <jiri@…> (2018-05-16 17:28:17)

git-committer:

Jiri Svoboda <jiri@…> (2018-05-17 08:29:01)

Message:

Fix block comment formatting (ccheck).

File:

• kernel/arch/amd64/src/fpu_context.c (modified) (1 diff)

kernel/arch/amd64/src/fpu_context.c

@@ -57 +57 @@
 {
         /* TODO: Zero all SSE, MMX etc. registers */
-        /* Default value of SCR register is 0x1f80,
-         * it masks all FPU exceptions*/
+        /*
+         * Default value of SCR register is 0x1f80,
+         * it masks all FPU exceptions
+         */
         asm volatile (
             "fninit\n"