Changeset 69146b93 in mainline for boot/arch/arm32/src/mm.c

Timestamp:

2012-11-26T19:02:45Z (11 years ago)

Author:

Adam Hraska <adam.hraska+hos@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

04552324

Parents:

5d230a30 (diff), 7462674 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merged mainline,1723.

File:

• boot/arch/arm32/src/mm.c (modified) (4 diffs)

boot/arch/arm32/src/mm.c

@@ -54 +54 @@
 {
         pte->descriptor_type = PTE_DESCRIPTOR_SECTION;
-        pte->bufferable = 0;
+        pte->bufferable = 1;
         pte->cacheable = 0;
-        pte->impl_specific = 0;
+        pte->xn = 0;
         pte->domain = 0;
         pte->should_be_zero_1 = 0;
-        pte->access_permission = PTE_AP_USER_NO_KERNEL_RW;
+        pte->access_permission_0 = PTE_AP_USER_NO_KERNEL_RW;
+        pte->tex = 0;
+        pte->access_permission_1 = 0;
+        pte->non_global = 0;
         pte->should_be_zero_2 = 0;
+        pte->non_secure = 0;
         pte->section_base_addr = frame;
 }
@@ -67 +71 @@
 static void init_boot_pt(void)
 {
-        pfn_t split_page = 0x800;
-        
+        const pfn_t split_page = PTL0_ENTRIES;
         /* Create 1:1 virtual-physical mapping (in lower 2 GB). */
         pfn_t page;
@@ -78 +81 @@
          * (upper 2 GB), physical addresses start from 0.
          */
+        /* BeagleBoard-xM (DM37x) memory starts at 2GB border,
+         * thus mapping only lower 2GB is not not enough.
+         * Map entire AS 1:1 instead and hope it works. */
         for (page = split_page; page < PTL0_ENTRIES; page++)
+#ifndef MACHINE_beagleboardxm
                 init_ptl0_section(&boot_pt[page], page - split_page);
+#else
+                init_ptl0_section(&boot_pt[page], page);
+#endif
         
         asm volatile (
@@ -95 +105 @@
                 /* Behave as a client of domains */
                 "ldr r0, =0x55555555\n"
-                "mcr p15, 0, r0, c3, c0, 0\n" 
+                "mcr p15, 0, r0, c3, c0, 0\n"
                 
+#ifdef PROCESSOR_armv7_a
+                /* Read Auxiliary control register */
+                "mrc p15, 0, r0, c1, c0, 1\n"
+                /* Mask to enable L2 cache */
+                "ldr r1, =0x00000002\n"
+                "orr r0, r0, r1\n"
+                /* Store Auxiliary control register */
+                "mrc p15, 0, r0, c1, c0, 1\n"
+#endif
                 /* Current settings */
                 "mrc p15, 0, r0, c1, c0, 0\n"
                 
+#ifdef PROCESSOR_armv7_a
+                /* Mask to enable paging, caching */
+                "ldr r1, =0x00000005\n"
+#else
                 /* Mask to enable paging */
                 "ldr r1, =0x00000001\n"
+#endif
                 "orr r0, r0, r1\n"