Changeset 666773c in mainline for kernel/arch/ia64/src/start.S
- Timestamp:
- 2008-12-31T15:33:29Z (15 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 9805cde
- Parents:
- d8c0dc5
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/ia64/src/start.S
rd8c0dc5 r666773c 33 33 34 34 #define RR_MASK (0xFFFFFFFF00000002) 35 #define RID_SHIFT 8 36 #define PS_SHIFT 2 37 38 #define KERNEL_TRANSLATION_I 0x0010000000000661 39 #define KERNEL_TRANSLATION_D 0x0010000000000661 40 #define KERNEL_TRANSLATION_VIO 0x0010000000000671 41 #define KERNEL_TRANSLATION_IO 0x00100FFFFC000671 42 #define KERNEL_TRANSLATION_FW 0x00100000F0000671 43 44 35 #define RID_SHIFT 8 36 #define PS_SHIFT 2 37 38 #define KERNEL_TRANSLATION_I 0x0010000000000661 39 #define KERNEL_TRANSLATION_D 0x0010000000000661 40 #define KERNEL_TRANSLATION_VIO 0x0010000000000671 41 #define KERNEL_TRANSLATION_IO 0x00100FFFFC000671 42 #define KERNEL_TRANSLATION_FW 0x00100000F0000671 45 43 46 44 .section K_TEXT_START, "ax" … … 52 50 .auto 53 51 54 #identifi self(CPU) in OS structures by ID / EID 55 mov r9=cr64 56 mov r10=1 57 movl r12=0xffffffff 58 movl r8=cpu_by_id_eid_list 59 and r8=r8,r12 60 shr r9=r9,16 61 add r8=r8,r9 62 st1 [r8]=r10 63 64 52 # Identify self(CPU) in OS structures by ID / EID 53 54 mov r9 = cr64 55 mov r10 = 1 56 movl r12 = 0xffffffff 57 movl r8 = cpu_by_id_eid_list 58 and r8 = r8, r12 59 shr r9 = r9, 16 60 add r8 = r8, r9 61 st1 [r8] = r10 65 62 66 63 mov psr.l = r0 … … 70 67 # Fill TR.i and TR.d using Region Register #VRN_KERNEL 71 68 72 73 69 movl r8 = (VRN_KERNEL << VRN_SHIFT) 74 70 mov r9 = rr[r8] 75 76 71 77 72 movl r10 = (RR_MASK) … … 80 75 or r9 = r10, r9 81 76 82 83 77 mov rr[r8] = r9 84 78 85 86 87 79 movl r8 = (VRN_KERNEL << VRN_SHIFT) 88 80 mov cr.ifa = r8 89 81 90 91 82 mov r11 = cr.itir ;; 92 83 movl r10 = (KERNEL_PAGE_WIDTH << PS_SHIFT);; 93 or r10 = r10 , r11;;84 or r10 = r10, r11 ;; 94 85 mov cr.itir = r10;; 95 86 96 97 87 movl r10 = (KERNEL_TRANSLATION_I) 98 88 itr.i itr[r0] = r10 99 100 101 89 movl r10 = (KERNEL_TRANSLATION_D) 102 90 itr.d dtr[r0] = r10 103 91 104 105 92 movl r7 = 1 106 93 movl r8 = (VRN_KERNEL << VRN_SHIFT) | VIO_OFFSET … … 109 96 itr.d dtr[r7] = r10 110 97 111 112 98 mov r11 = cr.itir ;; 113 99 movl r10 = ~0xfc;; 114 and r10 = r10 , r11;;100 and r10 = r10, r11 ;; 115 101 movl r11 = (IO_PAGE_WIDTH << PS_SHIFT);; 116 or r10 = r10 , r11;;102 or r10 = r10, r11 ;; 117 103 mov cr.itir = r10;; 118 119 104 120 105 movl r7 = 2 … … 124 109 itr.d dtr[r7] = r10 125 110 126 127 #setup mapping for fimware arrea (also SAPIC) 111 # Setup mapping for fimware arrea (also SAPIC) 112 128 113 mov r11 = cr.itir ;; 129 114 movl r10 = ~0xfc;; 130 and r10 = r10 , r11;;115 and r10 = r10, r11 ;; 131 116 movl r11 = (FW_PAGE_WIDTH << PS_SHIFT);; 132 or r10 = r10 , r11;;117 or r10 = r10, r11 ;; 133 118 mov cr.itir = r10;; 134 135 119 136 120 movl r7 = 3 … … 140 124 itr.d dtr[r7] = r10 141 125 142 143 144 145 146 # initialize PSR 126 # Initialize PSR 127 147 128 movl r10 = (PSR_DT_MASK | PSR_RT_MASK | PSR_IT_MASK | PSR_IC_MASK) /* Enable paging */ 148 129 mov r9 = psr 130 149 131 or r10 = r10, r9 150 132 mov cr.ipsr = r10 … … 156 138 157 139 .explicit 140 158 141 /* 159 142 * Return From Interupt is the only the way to fill upper half word of PSR. … … 161 144 rfi;; 162 145 146 163 147 .global paging_start 164 148 paging_start: … … 168 152 */ 169 153 170 # switch to register bank 1154 # Switch to register bank 1 171 155 bsw.1 172 156 173 #Am'I BSP or AP 174 movl r20=bsp_started;; 175 ld8 r20=[r20];; 176 cmp.eq p3,p2=r20,r0;; 177 157 # Am I BSP or AP? 158 movl r20 = bsp_started;; 159 ld8 r20 = [r20];; 160 cmp.eq p3, p2 = r20, r0;; 178 161 179 # initialize register stack162 # Initialize register stack 180 163 mov ar.rsc = r0 181 164 movl r8 = (VRN_KERNEL << VRN_SHIFT) ;; … … 183 166 loadrs 184 167 185 # initialize memory stack to some sane value168 # Initialize memory stack to some sane value 186 169 movl r12 = stack0 ;; 187 188 170 add r12 = -16, r12 /* allocate a scratch area on the stack */ 189 171 190 # initialize gp (Global Pointer) register172 # Initialize gp (Global Pointer) register 191 173 movl r20 = (VRN_KERNEL << VRN_SHIFT);; 192 174 or r20 = r20,r1;; … … 217 199 (p2) br.call.sptk.many b0 = b1 218 200 219 #Mark that BSP is on201 # Mark that BSP is on 220 202 mov r20=1;; 221 203 movl r21=bsp_started;; 222 204 st8 [r21]=r20;; 223 205 224 225 206 br.call.sptk.many b0 = arch_pre_main 226 207 … … 229 210 br.call.sptk.many b0 = b1 230 211 231 232 212 0: 233 213 br 0b … … 236 216 kernel_image_ap_start: 237 217 .auto 238 #identifi self(CPU) in OS structures by ID / EID 239 mov r9=cr64 240 mov r10=1 241 movl r12=0xffffffff 242 movl r8=cpu_by_id_eid_list 243 and r8=r8,r12 244 shr r9=r9,16 245 add r8=r8,r9 246 st1 [r8]=r10 218 219 # Identify self(CPU) in OS structures by ID / EID 220 221 mov r9 = cr64 222 mov r10 = 1 223 movl r12 = 0xffffffff 224 movl r8 = cpu_by_id_eid_list 225 and r8 = r8, r12 226 shr r9 = r9, 16 227 add r8 = r8, r9 228 st1 [r8] = r10 247 229 248 #wait for wakeup sychro signal (#3 in cpu_by_id_eid_list)230 # Wait for wakeup synchro signal (#3 in cpu_by_id_eid_list) 249 231 kernel_image_ap_start_loop: 250 movl r11 =kernel_image_ap_start_loop251 and r11 =r11,r12232 movl r11 = kernel_image_ap_start_loop 233 and r11 = r11, r12 252 234 mov b1 = r11 253 235 254 ld1 r20 =[r8];;255 movl r21 =3;;256 cmp.eq p2, p3=r20,r21;;257 (p3) br.call.sptk.many b0 = b1258 259 movl r11 =kernel_image_start260 and r11 =r11,r12261 236 ld1 r20 = [r8];; 237 movl r21 = 3;; 238 cmp.eq p2, p3 = r20, r21;; 239 (p3) br.call.sptk.many b0 = b1 240 241 movl r11 = kernel_image_start 242 and r11 = r11, r12 243 mov b1 = r11 262 244 br.call.sptk.many b0 = b1 263 245 … … 268 250 .space 8 269 251 270 271 252 .align 4096 272 253 .global cpu_by_id_eid_list … … 274 255 .space 65536 275 256 276
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