Changeset 666773c in mainline for kernel/arch/ia64/src/start.S


Ignore:
Timestamp:
2008-12-31T15:33:29Z (15 years ago)
Author:
Jakub Jermar <jakub@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
9805cde
Parents:
d8c0dc5
Message:

Humanitarian facelift for ia64.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/ia64/src/start.S

    rd8c0dc5 r666773c  
    3333
    3434#define RR_MASK (0xFFFFFFFF00000002)
    35 #define RID_SHIFT 8
    36 #define PS_SHIFT 2
    37 
    38 #define KERNEL_TRANSLATION_I  0x0010000000000661
    39 #define KERNEL_TRANSLATION_D  0x0010000000000661
    40 #define KERNEL_TRANSLATION_VIO 0x0010000000000671
    41 #define KERNEL_TRANSLATION_IO 0x00100FFFFC000671
    42 #define KERNEL_TRANSLATION_FW 0x00100000F0000671
    43 
    44 
     35#define RID_SHIFT       8
     36#define PS_SHIFT        2
     37
     38#define KERNEL_TRANSLATION_I    0x0010000000000661
     39#define KERNEL_TRANSLATION_D    0x0010000000000661
     40#define KERNEL_TRANSLATION_VIO  0x0010000000000671
     41#define KERNEL_TRANSLATION_IO   0x00100FFFFC000671
     42#define KERNEL_TRANSLATION_FW   0x00100000F0000671
    4543
    4644.section K_TEXT_START, "ax"
     
    5250        .auto
    5351
    54 #identifi self(CPU) in OS structures by ID / EID
    55         mov r9=cr64
    56         mov r10=1
    57         movl r12=0xffffffff
    58         movl r8=cpu_by_id_eid_list
    59         and r8=r8,r12
    60         shr r9=r9,16
    61         add r8=r8,r9
    62         st1 [r8]=r10
    63 
    64 
     52        # Identify self(CPU) in OS structures by ID / EID
     53
     54        mov r9 = cr64
     55        mov r10 = 1
     56        movl r12 = 0xffffffff
     57        movl r8 = cpu_by_id_eid_list
     58        and r8 = r8, r12
     59        shr r9 = r9, 16
     60        add r8 = r8, r9
     61        st1 [r8] = r10
    6562
    6663        mov psr.l = r0
     
    7067        # Fill TR.i and TR.d using Region Register #VRN_KERNEL
    7168
    72 
    7369        movl r8 = (VRN_KERNEL << VRN_SHIFT)
    7470        mov r9 = rr[r8]
    75 
    7671
    7772        movl r10 = (RR_MASK)
     
    8075        or  r9 = r10, r9
    8176
    82 
    8377        mov rr[r8] = r9
    8478
    85 
    86 
    8779        movl r8 = (VRN_KERNEL << VRN_SHIFT)
    8880        mov cr.ifa = r8
    8981
    90        
    9182        mov r11 = cr.itir ;;
    9283        movl r10 = (KERNEL_PAGE_WIDTH << PS_SHIFT);;
    93         or r10 =r10 , r11 ;;
     84        or r10 = r10, r11 ;;
    9485        mov cr.itir = r10;;
    9586
    96        
    9787        movl r10 = (KERNEL_TRANSLATION_I)
    9888        itr.i itr[r0] = r10
    99 
    100        
    10189        movl r10 = (KERNEL_TRANSLATION_D)
    10290        itr.d dtr[r0] = r10
    10391
    104 
    10592        movl r7 = 1
    10693        movl r8 = (VRN_KERNEL << VRN_SHIFT) | VIO_OFFSET
     
    10996        itr.d dtr[r7] = r10
    11097
    111 
    11298        mov r11 = cr.itir ;;
    11399        movl r10 = ~0xfc;;
    114         and r10 =r10 , r11 ;;
     100        and r10 = r10, r11 ;;
    115101        movl r11 = (IO_PAGE_WIDTH << PS_SHIFT);;
    116         or r10 =r10 , r11 ;;
     102        or r10 = r10, r11 ;;
    117103        mov cr.itir = r10;;
    118 
    119104
    120105        movl r7 = 2
     
    124109        itr.d dtr[r7] = r10
    125110
    126 
    127 #setup mapping for fimware arrea (also SAPIC)
     111        # Setup mapping for fimware arrea (also SAPIC)
     112
    128113        mov r11 = cr.itir ;;
    129114        movl r10 = ~0xfc;;
    130         and r10 =r10 , r11 ;;
     115        and r10 = r10, r11 ;;
    131116        movl r11 = (FW_PAGE_WIDTH << PS_SHIFT);;
    132         or r10 =r10 , r11 ;;
     117        or r10 = r10, r11 ;;
    133118        mov cr.itir = r10;;
    134 
    135119
    136120        movl r7 = 3
     
    140124        itr.d dtr[r7] = r10
    141125
    142 
    143 
    144 
    145 
    146         # initialize PSR
     126        # Initialize PSR
     127
    147128        movl r10 = (PSR_DT_MASK | PSR_RT_MASK | PSR_IT_MASK | PSR_IC_MASK)  /* Enable paging */
    148129        mov r9 = psr
     130
    149131        or r10 = r10, r9
    150132        mov cr.ipsr = r10
     
    156138
    157139        .explicit
     140
    158141        /*
    159142         * Return From Interupt is the only the way to fill upper half word of PSR.
     
    161144        rfi;;
    162145
     146
    163147.global paging_start
    164148paging_start:
     
    168152         */
    169153
    170         # switch to register bank 1
     154        # Switch to register bank 1
    171155        bsw.1
    172156
    173 #Am'I BSP or AP
    174         movl r20=bsp_started;;
    175         ld8 r20=[r20];;
    176         cmp.eq p3,p2=r20,r0;;
    177 
     157        # Am I BSP or AP?
     158        movl r20 = bsp_started;;
     159        ld8 r20 = [r20];;
     160        cmp.eq p3, p2 = r20, r0;;
    178161       
    179         # initialize register stack
     162        # Initialize register stack
    180163        mov ar.rsc = r0
    181164        movl r8 = (VRN_KERNEL << VRN_SHIFT) ;;
     
    183166        loadrs
    184167
    185         # initialize memory stack to some sane value
     168        # Initialize memory stack to some sane value
    186169        movl r12 = stack0 ;;
    187        
    188170        add r12 = -16, r12      /* allocate a scratch area on the stack */
    189171
    190         # initialize gp (Global Pointer) register
     172        # Initialize gp (Global Pointer) register
    191173        movl r20 = (VRN_KERNEL << VRN_SHIFT);;
    192174        or r20 = r20,r1;;
     
    217199(p2)    br.call.sptk.many b0 = b1
    218200
    219 #Mark that BSP is on
     201        # Mark that BSP is on
    220202        mov r20=1;;
    221203        movl r21=bsp_started;;
    222204        st8 [r21]=r20;;
    223205
    224 
    225206        br.call.sptk.many b0 = arch_pre_main
    226207
     
    229210        br.call.sptk.many b0 = b1
    230211
    231 
    2322120:
    233213        br 0b
     
    236216kernel_image_ap_start:
    237217        .auto
    238 #identifi self(CPU) in OS structures by ID / EID
    239         mov r9=cr64
    240         mov r10=1
    241         movl r12=0xffffffff
    242         movl r8=cpu_by_id_eid_list
    243         and r8=r8,r12
    244         shr r9=r9,16
    245         add r8=r8,r9
    246         st1 [r8]=r10
     218
     219        # Identify self(CPU) in OS structures by ID / EID
     220
     221        mov r9 = cr64
     222        mov r10 = 1
     223        movl r12 = 0xffffffff
     224        movl r8 = cpu_by_id_eid_list
     225        and r8 = r8, r12
     226        shr r9 = r9, 16
     227        add r8 = r8, r9
     228        st1 [r8] = r10
    247229       
    248 #wait for wakeup sychro signal (#3 in cpu_by_id_eid_list)
     230        # Wait for wakeup synchro signal (#3 in cpu_by_id_eid_list)
    249231kernel_image_ap_start_loop:
    250         movl r11=kernel_image_ap_start_loop
    251         and r11=r11,r12
     232        movl r11 = kernel_image_ap_start_loop
     233        and r11 = r11, r12
    252234        mov b1 = r11
    253235
    254         ld1 r20=[r8];;
    255         movl r21=3;;
    256         cmp.eq p2,p3=r20,r21;;
    257 (p3)br.call.sptk.many b0 = b1
    258 
    259         movl r11=kernel_image_start
    260         and r11=r11,r12
    261     mov b1 = r11
     236        ld1 r20 = [r8];;
     237        movl r21 = 3;;
     238        cmp.eq p2, p3 = r20, r21;;
     239(p3)    br.call.sptk.many b0 = b1
     240
     241        movl r11 = kernel_image_start
     242        and r11 = r11, r12
     243        mov b1 = r11
    262244        br.call.sptk.many b0 = b1
    263245
     
    268250.space 8
    269251
    270 
    271252.align 4096
    272253.global cpu_by_id_eid_list
     
    274255.space 65536
    275256
    276 
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