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Changeset 65eac7b in mainline


Ignore:
Timestamp:
2012-02-24T03:08:24Z (8 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
master
Children:
668a2e8
Parents:
4e30369
Message:

ohci: Use endain aware access to manipulate memory structures.

Enable work queues

Location:
uspace/drv/bus/usb/ohci
Files:
6 edited

Legend:

Unmodified
Added
Removed
  • uspace/drv/bus/usb/ohci/hc.c

    r4e30369 r65eac7b  
    515515
    516516        /* Enable queues */
    517 //      OHCI_SET(instance->registers->control, (C_PLE | C_IE | C_CLE | C_BLE));
    518 //      usb_log_debug("Queues enabled(%x).\n",
    519 //          OHCI_RD(instance->registers->control));
     517        OHCI_SET(instance->registers->control, (C_PLE | C_IE | C_CLE | C_BLE));
     518        usb_log_debug("Queues enabled(%x).\n",
     519            OHCI_RD(instance->registers->control));
    520520
    521521        /* Enable interrupts */
     
    596596
    597597        for (unsigned i = 0; i < 32; ++i) {
    598                 instance->hcca->int_ep[i] =
    599                     instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa;
     598                OHCI_WR(instance->hcca->int_ep[i],
     599                    instance->lists[USB_TRANSFER_INTERRUPT].list_head_pa);
    600600        }
    601601        usb_log_debug2("Interrupt HEADs set to: %p (%#" PRIx32 ").\n",
  • uspace/drv/bus/usb/ohci/hw_struct/endpoint_descriptor.c

    r4e30369 r65eac7b  
    5858                /* Mark as dead, used for dummy EDs at the beginning of
    5959                 * endpoint lists. */
    60                 instance->status = ED_STATUS_K_FLAG;
     60                OHCI_WR(instance->status, ED_STATUS_K_FLAG);
    6161                return;
    6262        }
     
    6565
    6666        /* Status: address, endpoint nr, direction mask and max packet size. */
    67         instance->status = 0
    68             | ((ep->address & ED_STATUS_FA_MASK) << ED_STATUS_FA_SHIFT)
     67        OHCI_WR(instance->status,
     68            ((ep->address & ED_STATUS_FA_MASK) << ED_STATUS_FA_SHIFT)
    6969            | ((ep->endpoint & ED_STATUS_EN_MASK) << ED_STATUS_EN_SHIFT)
    7070            | ((dir[ep->direction] & ED_STATUS_D_MASK) << ED_STATUS_D_SHIFT)
    7171            | ((ep->max_packet_size & ED_STATUS_MPS_MASK)
    72                 << ED_STATUS_MPS_SHIFT);
     72                << ED_STATUS_MPS_SHIFT));
    7373
    7474        /* Low speed flag */
    7575        if (ep->speed == USB_SPEED_LOW)
    76                 instance->status |= ED_STATUS_S_FLAG;
     76                OHCI_SET(instance->status, ED_STATUS_S_FLAG);
    7777
    7878        /* Isochronous format flag */
    7979        if (ep->transfer_type == USB_TRANSFER_ISOCHRONOUS)
    80                 instance->status |= ED_STATUS_F_FLAG;
     80                OHCI_SET(instance->status, ED_STATUS_F_FLAG);
    8181
    8282        /* Set TD to the list */
    8383        const uintptr_t pa = addr_to_phys(td);
    84         instance->td_head = pa & ED_TDHEAD_PTR_MASK;
    85         instance->td_tail = pa & ED_TDTAIL_PTR_MASK;
     84        OHCI_WR(instance->td_head, pa & ED_TDHEAD_PTR_MASK);
     85        OHCI_WR(instance->td_tail, pa & ED_TDTAIL_PTR_MASK);
    8686
    8787        /* Set toggle bit */
    8888        if (ep->toggle)
    89                 instance->td_head |= ED_TDHEAD_TOGGLE_CARRY;
     89                OHCI_SET(instance->td_head, ED_TDHEAD_TOGGLE_CARRY);
    9090
    9191}
  • uspace/drv/bus/usb/ohci/hw_struct/endpoint_descriptor.h

    r4e30369 r65eac7b  
    4040#include <usb/host/endpoint.h>
    4141
     42#include "../ohci_regs.h"
    4243#include "../utils/malloc32.h"
    4344#include "transfer_descriptor.h"
     
    116117{
    117118        assert(instance);
    118         return (instance->td_head & ED_TDHEAD_HALTED_FLAG)
    119             || (instance->status & ED_STATUS_K_FLAG);
     119        return (OHCI_RD(instance->td_head) & ED_TDHEAD_HALTED_FLAG)
     120            || (OHCI_RD(instance->status) & ED_STATUS_K_FLAG);
     121}
     122
     123static inline void ed_clear_halt(ed_t *instance)
     124{
     125        assert(instance);
     126        OHCI_CLR(instance->td_head, ED_TDHEAD_HALTED_FLAG);
    120127}
    121128
     
    128135{
    129136        assert(instance);
    130         return (instance->td_head & ED_TDHEAD_PTR_MASK)
    131             != (instance->td_tail & ED_TDTAIL_PTR_MASK);
     137        return (OHCI_RD(instance->td_head) & ED_TDHEAD_PTR_MASK)
     138            != (OHCI_RD(instance->td_tail) & ED_TDTAIL_PTR_MASK);
    132139}
    133140
     
    141148        assert(instance);
    142149        const uintptr_t pa = addr_to_phys(td);
    143         instance->td_tail = pa & ED_TDTAIL_PTR_MASK;
     150        OHCI_WR(instance->td_tail, pa & ED_TDTAIL_PTR_MASK);
     151}
     152
     153static inline uint32_t ed_tail_td(const ed_t *instance)
     154{
     155        assert(instance);
     156        return OHCI_RD(instance->td_tail) & ED_TDTAIL_PTR_MASK;
     157}
     158
     159static inline uint32_t ed_head_td(const ed_t *instance)
     160{
     161        assert(instance);
     162        return OHCI_RD(instance->td_head) & ED_TDHEAD_PTR_MASK;
    144163}
    145164
     
    155174        const uint32_t pa = addr_to_phys(next);
    156175        assert((pa & ED_NEXT_PTR_MASK) << ED_NEXT_PTR_SHIFT == pa);
    157         instance->next = pa;
     176        OHCI_WR(instance->next, pa);
    158177}
    159178
     
    166185{
    167186        assert(instance);
    168         return (instance->td_head & ED_TDHEAD_TOGGLE_CARRY) ? 1 : 0;
     187        return (OHCI_RD(instance->td_head) & ED_TDHEAD_TOGGLE_CARRY) ? 1 : 0;
    169188}
    170189
     
    178197        assert(instance);
    179198        if (toggle) {
    180                 instance->td_head |= ED_TDHEAD_TOGGLE_CARRY;
     199                OHCI_SET(instance->td_head, ED_TDHEAD_TOGGLE_CARRY);
    181200        } else {
    182201                /* Clear halted flag when reseting toggle TODO: Why? */
    183                 instance->td_head &= ~ED_TDHEAD_TOGGLE_CARRY;
    184                 instance->td_head &= ~ED_TDHEAD_HALTED_FLAG;
     202                OHCI_CLR(instance->td_head, ED_TDHEAD_TOGGLE_CARRY);
     203                OHCI_CLR(instance->td_head, ED_TDHEAD_HALTED_FLAG);
    185204        }
    186205}
  • uspace/drv/bus/usb/ohci/hw_struct/transfer_descriptor.c

    r4e30369 r65eac7b  
    3333 */
    3434#include <usb/usb.h>
     35#include <mem.h>
     36#include "../utils/malloc32.h"
    3537#include "transfer_descriptor.h"
    3638
     
    5860        bzero(instance, sizeof(td_t));
    5961        /* Set PID and Error code */
    60         instance->status = 0
    61             | ((dir[direction] & TD_STATUS_DP_MASK) << TD_STATUS_DP_SHIFT)
    62             | ((CC_NOACCESS2 & TD_STATUS_CC_MASK) << TD_STATUS_CC_SHIFT);
     62        OHCI_WR(instance->status,
     63            ((dir[direction] & TD_STATUS_DP_MASK) << TD_STATUS_DP_SHIFT)
     64            | ((CC_NOACCESS2 & TD_STATUS_CC_MASK) << TD_STATUS_CC_SHIFT));
    6365
    6466        if (toggle == 0 || toggle == 1) {
    6567                /* Set explicit toggle bit */
    66                 instance->status |= TD_STATUS_T_USE_TD_FLAG;
    67                 instance->status |= toggle ? TD_STATUS_T_FLAG : 0;
     68                OHCI_SET(instance->status, TD_STATUS_T_USE_TD_FLAG);
     69                OHCI_SET(instance->status, toggle ? TD_STATUS_T_FLAG : 0);
    6870        }
    6971
    7072        /* Alow less data on input. */
    7173        if (dir == USB_DIRECTION_IN) {
    72                 instance->status |= TD_STATUS_ROUND_FLAG;
     74                OHCI_SET(instance->status, TD_STATUS_ROUND_FLAG);
    7375        }
    7476
    7577        if (buffer != NULL) {
    7678                assert(size != 0);
    77                 instance->cbp = addr_to_phys(buffer);
    78                 instance->be = addr_to_phys(buffer + size - 1);
     79                OHCI_WR(instance->cbp, addr_to_phys(buffer));
     80                OHCI_WR(instance->be, addr_to_phys(buffer + size - 1));
    7981        }
    8082
    81         instance->next = addr_to_phys(next) & TD_NEXT_PTR_MASK;
     83        OHCI_WR(instance->next, addr_to_phys(next) & TD_NEXT_PTR_MASK);
    8284
    8385}
  • uspace/drv/bus/usb/ohci/hw_struct/transfer_descriptor.h

    r4e30369 r65eac7b  
    3838#include <stdint.h>
    3939
    40 #include "../utils/malloc32.h"
     40#include "../ohci_regs.h"
    4141#include "completion_codes.h"
    4242
     
    100100{
    101101        assert(instance);
    102         const int cc =
    103             (instance->status >> TD_STATUS_CC_SHIFT) & TD_STATUS_CC_MASK;
     102        const int cc =(OHCI_RD(instance->status)
     103            >> TD_STATUS_CC_SHIFT) & TD_STATUS_CC_MASK;
    104104        /* This value is changed on transfer completion,
    105105         * either to CC_NOERROR or and error code.
     
    119119{
    120120        assert(instance);
    121         const int cc =
    122             (instance->status >> TD_STATUS_CC_SHIFT) & TD_STATUS_CC_MASK;
     121        const int cc = (OHCI_RD(instance->status)
     122            >> TD_STATUS_CC_SHIFT) & TD_STATUS_CC_MASK;
    123123        return cc_to_rc(cc);
    124124}
     
    136136                return 0;
    137137        /* Buffer end points to the last byte of transfer buffer, so add 1 */
    138         return instance->be - instance->cbp + 1;
     138        return OHCI_RD(instance->be) - OHCI_RD(instance->cbp) + 1;
    139139}
    140140#endif
  • uspace/drv/bus/usb/ohci/ohci_batch.c

    r4e30369 r65eac7b  
    231231
    232232                        /* Check TD assumption */
    233                         const uint32_t pa =
    234                             addr_to_phys(ohci_batch->tds[leave_td]);
    235                         assert((ohci_batch->ed->td_head & ED_TDHEAD_PTR_MASK)
    236                             == pa);
    237 
     233                        assert(ed_head_td(ohci_batch->ed) ==
     234                            addr_to_phys(ohci_batch->tds[leave_td]));
     235
     236                        /* Set tail to the same TD */
    238237                        ed_set_tail_td(ohci_batch->ed,
    239238                            ohci_batch->tds[leave_td]);
    240239
    241240                        /* Clear possible ED HALT */
    242                         ohci_batch->ed->td_head &= ~ED_TDHEAD_HALTED_FLAG;
     241                        ed_clear_halt(ohci_batch->ed);
    243242                        break;
    244243                }
     
    253252
    254253        /* Make sure that we are leaving the right TD behind */
    255         const uint32_t pa = addr_to_phys(ohci_ep->td);
    256         assert(pa == (ohci_batch->ed->td_head & ED_TDHEAD_PTR_MASK));
    257         assert(pa == (ohci_batch->ed->td_tail & ED_TDTAIL_PTR_MASK));
     254        assert(addr_to_phys(ohci_ep->td) == ed_head_td(ohci_batch->ed));
     255        assert(addr_to_phys(ohci_ep->td) == ed_tail_td(ohci_batch->ed));
     256//      const uint32_t pa = addr_to_phys(ohci_ep->td);
     257//      assert(pa == (ohci_batch->ed->td_head & ED_TDHEAD_PTR_MASK));
     258//      assert(pa == (ohci_batch->ed->td_tail & ED_TDTAIL_PTR_MASK));
    258259
    259260        return true;
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