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Changeset 61b5cf0c in mainline


Ignore:
Timestamp:
2013-01-06T23:24:44Z (9 years ago)
Author:
Jan Vesely <jano.vesely@…>
Branches:
lfn, master
Children:
813b024
Parents:
b4b3a4cb
Message:

arm32: More info about coprocessors.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • kernel/arch/arm32/src/fpu_context.c

    rb4b3a4cb r61b5cf0c  
    6666        CPACR_CP10_USER_ACCESS = CPACR_CP10_MASK,
    6767        CPACR_CP11_USER_ACCESS = CPACR_CP11_MASK,
     68        NSACR_CP10_FLAG = 1 << 10,
     69        NSACR_CP11_FLAG = 1 << 11,
    6870};
    6971
     
    133135}
    134136
     137/** Enable coprocessor access. Turn both non-secure mode bit and generic access.
     138 * Cortex A8 Manual says:
     139 * "You must execute an Instruction Memory Barrier (IMB) sequence immediately
     140 * after an update of the Coprocessor Access Control Register, see Memory
     141 * Barriers in the ARM Architecture Reference Manual. You must not attempt to
     142 * execute any instructions that are affected by the change of access rights
     143 * between the IMB sequence and the register update."
     144 * Cortex a8 TRM ch. 3.2.27. c1, Coprocessor Access Control Register
     145 *
     146 * @note do we need to call secure monitor here?
     147 */
    135148static void fpu_enable_coprocessor_access()
    136149{
     150        uint32_t cpr;
     151        asm volatile("MRC p15, 0, %0, c1, c1, 0" : "=r" (cpr)::);
     152        if (cpr & 1)
     153                printf("We are in unsecure state, we can't change access\n");
     154
     155        /* Allow non-secure access */
     156        uint32_t nsacr;
     157        asm volatile ("mrc p15, 0, %0, c1, c1, 2" :"=r" (nsacr)::);
     158        /* FPU needs access to coprocessor 10 and 11.
     159         * Moreover, they need to have same access enabled */
     160        nsacr |= NSACR_CP10_FLAG | NSACR_CP11_FLAG;
     161        asm volatile ("mcr p15, 0, %0, c1, c1, 2" :"=r" (nsacr)::);
     162
     163#ifdef MACHINE_beagleboardxm
     164        asm volatile ("isb" ::: "memory" );
     165#endif
     166
     167        /* Allow coprocessor access */
    137168        uint32_t cpacr;
    138169        asm volatile ("mrc p15, 0, %0, c1, c0, 2" :"=r" (cpacr)::);
     
    142173        cpacr |= CPACR_CP11_USER_ACCESS;
    143174        asm volatile ("mcr p15, 0, %0, c1, c0, 2" :"=r" (cpacr)::);
     175
     176#ifdef MACHINE_beagleboardxm
     177        asm volatile ("isb" ::: "memory" );
     178#endif
    144179}
    145180
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