Changeset 61b5cf0c in mainline for kernel/arch/arm32/src/fpu_context.c

Timestamp:

2013-01-06T23:24:44Z (11 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

813b024

Parents:

b4b3a4cb

Message:

arm32: More info about coprocessors.

File:

• kernel/arch/arm32/src/fpu_context.c (modified) (3 diffs)

kernel/arch/arm32/src/fpu_context.c

@@ -66 +66 @@
         CPACR_CP10_USER_ACCESS = CPACR_CP10_MASK,
         CPACR_CP11_USER_ACCESS = CPACR_CP11_MASK,
+        NSACR_CP10_FLAG = 1 << 10,
+        NSACR_CP11_FLAG = 1 << 11,
 };
 
@@ -133 +135 @@
 }
 
+/** Enable coprocessor access. Turn both non-secure mode bit and generic access.
+ * Cortex A8 Manual says:
+ * "You must execute an Instruction Memory Barrier (IMB) sequence immediately
+ * after an update of the Coprocessor Access Control Register, see Memory
+ * Barriers in the ARM Architecture Reference Manual. You must not attempt to
+ * execute any instructions that are affected by the change of access rights
+ * between the IMB sequence and the register update."
+ * Cortex a8 TRM ch. 3.2.27. c1, Coprocessor Access Control Register
+ *
+ * @note do we need to call secure monitor here?
+ */
 static void fpu_enable_coprocessor_access()
 {
+        uint32_t cpr;
+        asm volatile("MRC p15, 0, %0, c1, c1, 0" : "=r" (cpr)::);
+        if (cpr & 1)
+                printf("We are in unsecure state, we can't change access\n");
+
+        /* Allow non-secure access */
+        uint32_t nsacr;
+        asm volatile ("mrc p15, 0, %0, c1, c1, 2" :"=r" (nsacr)::);
+        /* FPU needs access to coprocessor 10 and 11.
+         * Moreover, they need to have same access enabled */
+        nsacr |= NSACR_CP10_FLAG | NSACR_CP11_FLAG;
+        asm volatile ("mcr p15, 0, %0, c1, c1, 2" :"=r" (nsacr)::);
+
+#ifdef MACHINE_beagleboardxm
+        asm volatile ("isb" ::: "memory" );
+#endif
+
+        /* Allow coprocessor access */
         uint32_t cpacr;
         asm volatile ("mrc p15, 0, %0, c1, c0, 2" :"=r" (cpacr)::);
@@ -142 +173 @@
         cpacr |= CPACR_CP11_USER_ACCESS;
         asm volatile ("mcr p15, 0, %0, c1, c0, 2" :"=r" (cpacr)::);
+
+#ifdef MACHINE_beagleboardxm
+        asm volatile ("isb" ::: "memory" );
+#endif
 }