Changeset 5856b627 in mainline for kernel/arch/arm32/include/arch/mm/page_armv6.h

Timestamp:

2013-08-20T12:36:48Z (11 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

26e2de3

Parents:

0ee999d (diff), 4da8fdb (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Mainline changes.

File:

• kernel/arch/arm32/include/arch/mm/page_armv6.h (modified) (7 diffs)

kernel/arch/arm32/include/arch/mm/page_armv6.h

@@ -40 +40 @@
 #error "Do not include arch specific page.h directly use generic page.h instead"
 #endif
+
 
 /* Macros for querying the last-level PTE entries. */
@@ -125 +126 @@
 #define PTE_DESCRIPTOR_SMALL_PAGE_NX    3
 
-/** Sets the address of level 0 page table.
- *
- * @param pt Pointer to the page table to set.
- *
- */
-NO_TRACE static inline void set_ptl0_addr(pte_t *pt)
-{
-        asm volatile (
-                "mcr p15, 0, %[pt], c2, c0, 0\n"
-                :: [pt] "r" (pt)
-        );
-}
+
+/**
+ * For an ARMv7 implementation that does not include the Large Physical Address Extension,
+ * and in implementations of architecture versions before ARMv7, if the translation tables
+ * are held in Write-Back Cacheable memory, the caches must be cleaned to the point of
+ * unification after writing to the translation tables and before the DSB instruction. This
+ * ensures that the updated translation table are visible to a hardware translation table walk.
+ *
+ * Therefore, an example instruction sequence for writing a translation table entry,
+ * covering changes to the instruction
+ * or data mappings in a uniprocessor system is:
+ * STR rx, [Translation table entry]
+ * ; write new entry to the translation table
+ * Clean cache line [Translation table entry] : This operation is not required with the
+ * ; Multiprocessing Extensions.
+ * DSB
+ * ; ensures visibility of the data cleaned from the D Cache
+ * Invalidate TLB entry by MVA (and ASID if non-global) [page address]
+ * Invalidate BTC
+ * DSB
+ * ; ensure completion of the Invalidate TLB operation
+ * ISB
+ * ; ensure table changes visible to instruction fetch
+ *
+ * ARM Architecture reference chp. B3.10.1 p. B3-1375
+ * @note: see TTRB0/1 for pt memory type
+ */
+#define pt_coherence_m(pt, count) \
+do { \
+        for (unsigned i = 0; i < count; ++i) \
+                DCCMVAU_write((uintptr_t)(pt + i)); \
+        read_barrier(); \
+} while (0)
 
 
@@ -206 +228 @@
                 p->ns = 0;
         }
+        pt_coherence(p);
 }
 
@@ -232 +255 @@
                         p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE_NX;
         }
-        
-        /* tex=0 buf=1 and cache=1 => normal memory
-         * tex=0 buf=1 and cache=0 => shareable device mmio
-         */
-        p->cacheable = (flags & PAGE_CACHEABLE);
-        p->bufferable = 1;
-        p->tex = 0;
+
+        if (flags & PAGE_CACHEABLE) {
+                /*
+                 * Write-through, no write-allocate memory, see ch. B3.8.2
+                 * (p. B3-1358) of ARM Architecture reference manual.
+                 * Make sure the memory type is correct, and in sync with:
+                 * init_boot_pt (boot/arch/arm32/src/mm.c)
+                 * init_ptl0_section (boot/arch/arm32/src/mm.c)
+                 * set_ptl0_addr (kernel/arch/arm32/include/arch/mm/page.h)
+                 */
+                p->tex = 5;
+                p->cacheable = 0;
+                p->bufferable = 1;
+        } else {
+                /*
+                 * Shareable device memory, see ch. B3.8.2 (p. B3-1358) of
+                 * ARM Architecture reference manual.
+                 */
+                p->tex = 0;
+                p->cacheable = 0;
+                p->bufferable = 1;
+        }
         
         /* Shareable is ignored for devices (non-cacheable),
-         * turn it on for normal memory. */
-        p->shareable = 1;
+         * turn it off for normal memory. */
+        p->shareable = 0;
         
         p->non_global = !(flags & PAGE_GLOBAL);
@@ -256 +294 @@
                         p->access_permission_1 = PTE_AP1_RO;
         }
+        pt_coherence(p);
 }
 
@@ -264 +303 @@
         p->should_be_zero_0 = 0;
         p->should_be_zero_1 = 0;
-        write_barrier();
         p->descriptor_type = PTE_DESCRIPTOR_COARSE_TABLE;
+        pt_coherence(p);
 }
 
@@ -273 +312 @@
 
         p->descriptor_type = PTE_DESCRIPTOR_SMALL_PAGE;
+        pt_coherence(p);
 }