Changeset 56d5c7f in mainline for kernel/arch/mips32/src/asm.S
- Timestamp:
- 2009-03-06T09:59:38Z (15 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- b11ee88
- Parents:
- bc0bb7c
- File:
-
- 1 edited
-
kernel/arch/mips32/src/asm.S (modified) (5 diffs)
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/mips32/src/asm.S
rbc0bb7c r56d5c7f 32 32 33 33 .macro cp0_read reg 34 mfc0 $2, \reg34 mfc0 $2, \reg 35 35 j $31 36 36 nop … … 38 38 39 39 .macro cp0_write reg 40 mtc0 $4, \reg40 mtc0 $4, \reg 41 41 j $31 42 42 nop … … 72 72 memcpy_from_uspace: 73 73 memcpy_to_uspace: 74 move $t2,$a0 # save dst 75 addiu $v0,$a1,3 76 li $v1,-4 # 0xfffffffffffffffc 77 and $v0,$v0,$v1 78 beq $a1,$v0,3f 79 move $t0,$a0 80 81 0: 82 beq $a2,$zero,2f 83 move $a3,$zero 84 85 1: 86 addu $v0,$a1,$a3 87 lbu $a0,0($v0) 88 addu $v1,$t0,$a3 89 addiu $a3,$a3,1 90 bne $a3,$a2,1b 91 sb $a0,0($v1) 92 93 2: 94 jr $ra 95 move $v0,$t2 96 97 3: 98 addiu $v0,$a0,3 99 and $v0,$v0,$v1 100 bne $a0,$v0,0b 101 srl $t1,$a2,2 102 103 beq $t1,$zero,5f 104 move $a3,$zero 105 106 move $a3,$zero 107 move $a0,$zero 108 4: 109 addu $v0,$a1,$a0 110 lw $v1,0($v0) 111 addiu $a3,$a3,1 112 addu $v0,$t0,$a0 113 sw $v1,0($v0) 114 bne $a3,$t1,4b 115 addiu $a0,$a0,4 116 117 5: 118 andi $a2,$a2,0x3 119 beq $a2,$zero,2b 120 nop 121 122 sll $v0,$a3,2 123 addu $t1,$v0,$t0 124 move $a3,$zero 125 addu $t0,$v0,$a1 126 6: 127 addu $v0,$t0,$a3 128 lbu $a0,0($v0) 129 addu $v1,$t1,$a3 130 addiu $a3,$a3,1 131 bne $a3,$a2,6b 132 sb $a0,0($v1) 133 134 jr $ra 135 move $v0,$t2 74 move $t2, $a0 # save dst 75 76 addiu $v0, $a1, 3 77 li $v1, -4 # 0xfffffffffffffffc 78 and $v0, $v0, $v1 79 beq $a1, $v0, 3f 80 move $t0, $a0 81 82 0: 83 beq $a2, $zero, 2f 84 move $a3, $zero 85 86 1: 87 addu $v0, $a1, $a3 88 lbu $a0, 0($v0) 89 addu $v1, $t0, $a3 90 addiu $a3, $a3, 1 91 bne $a3, $a2, 1b 92 sb $a0, 0($v1) 93 94 2: 95 jr $ra 96 move $v0, $t2 97 98 3: 99 addiu $v0, $a0, 3 100 and $v0, $v0, $v1 101 bne $a0, $v0, 0b 102 srl $t1, $a2, 2 103 104 beq $t1, $zero, 5f 105 move $a3, $zero 106 107 move $a3, $zero 108 move $a0, $zero 109 110 4: 111 addu $v0, $a1, $a0 112 lw $v1, 0($v0) 113 addiu $a3, $a3, 1 114 addu $v0, $t0, $a0 115 sw $v1, 0($v0) 116 bne $a3, $t1, 4b 117 addiu $a0, $a0, 4 118 119 5: 120 andi $a2, $a2, 0x3 121 beq $a2, $zero, 2b 122 nop 123 124 sll $v0, $a3, 2 125 addu $t1, $v0, $t0 126 move $a3, $zero 127 addu $t0, $v0, $a1 128 129 6: 130 addu $v0, $t0, $a3 131 lbu $a0, 0($v0) 132 addu $v1, $t1, $a3 133 addiu $a3, $a3, 1 134 bne $a3, $a2, 6b 135 sb $a0, 0($v1) 136 137 jr $ra 138 move $v0, $t2 136 139 137 140 memcpy_from_uspace_failover_address: 138 141 memcpy_to_uspace_failover_address: 139 jr 140 move 142 jr $ra 143 move $v0, $zero 141 144 142 145 143 146 144 147 .macro fpu_gp_save reg ctx 145 mfc1 $t0, $\reg146 sw $t0, \reg *4(\ctx)148 mfc1 $t0, $\reg 149 sw $t0, \reg * 4(\ctx) 147 150 .endm 148 151 149 152 .macro fpu_gp_restore reg ctx 150 lw $t0, \reg *4(\ctx)151 mtc1 $t0, $\reg153 lw $t0, \reg * 4(\ctx) 154 mtc1 $t0, $\reg 152 155 .endm 153 156 154 157 .macro fpu_ct_save reg ctx 155 cfc1 $t0, $1156 sw $t0, (\reg +32)*4(\ctx)158 cfc1 $t0, $1 159 sw $t0, (\reg + 32) * 4(\ctx) 157 160 .endm 158 161 159 162 .macro fpu_ct_restore reg ctx 160 lw $t0, (\reg +32)*4(\ctx)161 ctc1 $t0, $\reg163 lw $t0, (\reg + 32) * 4(\ctx) 164 ctc1 $t0, $\reg 162 165 .endm 163 166 … … 166 169 fpu_context_save: 167 170 #ifdef CONFIG_FPU 168 fpu_gp_save 0, $a0169 fpu_gp_save 1, $a0170 fpu_gp_save 2, $a0171 fpu_gp_save 3, $a0172 fpu_gp_save 4, $a0173 fpu_gp_save 5, $a0174 fpu_gp_save 6, $a0175 fpu_gp_save 7, $a0176 fpu_gp_save 8, $a0177 fpu_gp_save 9, $a0178 fpu_gp_save 10, $a0179 fpu_gp_save 11, $a0180 fpu_gp_save 12, $a0181 fpu_gp_save 13, $a0182 fpu_gp_save 14, $a0183 fpu_gp_save 15, $a0184 fpu_gp_save 16, $a0185 fpu_gp_save 17, $a0186 fpu_gp_save 18, $a0187 fpu_gp_save 19, $a0188 fpu_gp_save 20, $a0189 fpu_gp_save 21, $a0190 fpu_gp_save 22, $a0191 fpu_gp_save 23, $a0192 fpu_gp_save 24, $a0193 fpu_gp_save 25, $a0194 fpu_gp_save 26, $a0195 fpu_gp_save 27, $a0196 fpu_gp_save 28, $a0197 fpu_gp_save 29, $a0198 fpu_gp_save 30, $a0199 fpu_gp_save 31, $a0200 201 fpu_ct_save 1, $a0202 fpu_ct_save 2, $a0203 fpu_ct_save 3, $a0204 fpu_ct_save 4, $a0205 fpu_ct_save 5, $a0206 fpu_ct_save 6, $a0207 fpu_ct_save 7, $a0208 fpu_ct_save 8, $a0209 fpu_ct_save 9, $a0210 fpu_ct_save 10, $a0211 fpu_ct_save 11, $a0212 fpu_ct_save 12, $a0213 fpu_ct_save 13, $a0214 fpu_ct_save 14, $a0215 fpu_ct_save 15, $a0216 fpu_ct_save 16, $a0217 fpu_ct_save 17, $a0218 fpu_ct_save 18, $a0219 fpu_ct_save 19, $a0220 fpu_ct_save 20, $a0221 fpu_ct_save 21, $a0222 fpu_ct_save 22, $a0223 fpu_ct_save 23, $a0224 fpu_ct_save 24, $a0225 fpu_ct_save 25, $a0226 fpu_ct_save 26, $a0227 fpu_ct_save 27, $a0228 fpu_ct_save 28, $a0229 fpu_ct_save 29, $a0230 fpu_ct_save 30, $a0231 fpu_ct_save 31, $a0232 #endif 171 fpu_gp_save 0, $a0 172 fpu_gp_save 1, $a0 173 fpu_gp_save 2, $a0 174 fpu_gp_save 3, $a0 175 fpu_gp_save 4, $a0 176 fpu_gp_save 5, $a0 177 fpu_gp_save 6, $a0 178 fpu_gp_save 7, $a0 179 fpu_gp_save 8, $a0 180 fpu_gp_save 9, $a0 181 fpu_gp_save 10, $a0 182 fpu_gp_save 11, $a0 183 fpu_gp_save 12, $a0 184 fpu_gp_save 13, $a0 185 fpu_gp_save 14, $a0 186 fpu_gp_save 15, $a0 187 fpu_gp_save 16, $a0 188 fpu_gp_save 17, $a0 189 fpu_gp_save 18, $a0 190 fpu_gp_save 19, $a0 191 fpu_gp_save 20, $a0 192 fpu_gp_save 21, $a0 193 fpu_gp_save 22, $a0 194 fpu_gp_save 23, $a0 195 fpu_gp_save 24, $a0 196 fpu_gp_save 25, $a0 197 fpu_gp_save 26, $a0 198 fpu_gp_save 27, $a0 199 fpu_gp_save 28, $a0 200 fpu_gp_save 29, $a0 201 fpu_gp_save 30, $a0 202 fpu_gp_save 31, $a0 203 204 fpu_ct_save 1, $a0 205 fpu_ct_save 2, $a0 206 fpu_ct_save 3, $a0 207 fpu_ct_save 4, $a0 208 fpu_ct_save 5, $a0 209 fpu_ct_save 6, $a0 210 fpu_ct_save 7, $a0 211 fpu_ct_save 8, $a0 212 fpu_ct_save 9, $a0 213 fpu_ct_save 10, $a0 214 fpu_ct_save 11, $a0 215 fpu_ct_save 12, $a0 216 fpu_ct_save 13, $a0 217 fpu_ct_save 14, $a0 218 fpu_ct_save 15, $a0 219 fpu_ct_save 16, $a0 220 fpu_ct_save 17, $a0 221 fpu_ct_save 18, $a0 222 fpu_ct_save 19, $a0 223 fpu_ct_save 20, $a0 224 fpu_ct_save 21, $a0 225 fpu_ct_save 22, $a0 226 fpu_ct_save 23, $a0 227 fpu_ct_save 24, $a0 228 fpu_ct_save 25, $a0 229 fpu_ct_save 26, $a0 230 fpu_ct_save 27, $a0 231 fpu_ct_save 28, $a0 232 fpu_ct_save 29, $a0 233 fpu_ct_save 30, $a0 234 fpu_ct_save 31, $a0 235 #endif 233 236 j $ra 234 237 nop … … 237 240 fpu_context_restore: 238 241 #ifdef CONFIG_FPU 239 fpu_gp_restore 0, $a0240 fpu_gp_restore 1, $a0241 fpu_gp_restore 2, $a0242 fpu_gp_restore 3, $a0243 fpu_gp_restore 4, $a0244 fpu_gp_restore 5, $a0245 fpu_gp_restore 6, $a0246 fpu_gp_restore 7, $a0247 fpu_gp_restore 8, $a0248 fpu_gp_restore 9, $a0249 fpu_gp_restore 10, $a0250 fpu_gp_restore 11, $a0251 fpu_gp_restore 12, $a0252 fpu_gp_restore 13, $a0253 fpu_gp_restore 14, $a0254 fpu_gp_restore 15, $a0255 fpu_gp_restore 16, $a0256 fpu_gp_restore 17, $a0257 fpu_gp_restore 18, $a0258 fpu_gp_restore 19, $a0259 fpu_gp_restore 20, $a0260 fpu_gp_restore 21, $a0261 fpu_gp_restore 22, $a0262 fpu_gp_restore 23, $a0263 fpu_gp_restore 24, $a0264 fpu_gp_restore 25, $a0265 fpu_gp_restore 26, $a0266 fpu_gp_restore 27, $a0267 fpu_gp_restore 28, $a0268 fpu_gp_restore 29, $a0269 fpu_gp_restore 30, $a0270 fpu_gp_restore 31, $a0271 272 fpu_ct_restore 1, $a0273 fpu_ct_restore 2, $a0274 fpu_ct_restore 3, $a0275 fpu_ct_restore 4, $a0276 fpu_ct_restore 5, $a0277 fpu_ct_restore 6, $a0278 fpu_ct_restore 7, $a0279 fpu_ct_restore 8, $a0280 fpu_ct_restore 9, $a0281 fpu_ct_restore 10, $a0282 fpu_ct_restore 11, $a0283 fpu_ct_restore 12, $a0284 fpu_ct_restore 13, $a0285 fpu_ct_restore 14, $a0286 fpu_ct_restore 15, $a0287 fpu_ct_restore 16, $a0288 fpu_ct_restore 17, $a0289 fpu_ct_restore 18, $a0290 fpu_ct_restore 19, $a0291 fpu_ct_restore 20, $a0292 fpu_ct_restore 21, $a0293 fpu_ct_restore 22, $a0294 fpu_ct_restore 23, $a0295 fpu_ct_restore 24, $a0296 fpu_ct_restore 25, $a0297 fpu_ct_restore 26, $a0298 fpu_ct_restore 27, $a0299 fpu_ct_restore 28, $a0300 fpu_ct_restore 29, $a0301 fpu_ct_restore 30, $a0302 fpu_ct_restore 31, $a0303 #endif 242 fpu_gp_restore 0, $a0 243 fpu_gp_restore 1, $a0 244 fpu_gp_restore 2, $a0 245 fpu_gp_restore 3, $a0 246 fpu_gp_restore 4, $a0 247 fpu_gp_restore 5, $a0 248 fpu_gp_restore 6, $a0 249 fpu_gp_restore 7, $a0 250 fpu_gp_restore 8, $a0 251 fpu_gp_restore 9, $a0 252 fpu_gp_restore 10, $a0 253 fpu_gp_restore 11, $a0 254 fpu_gp_restore 12, $a0 255 fpu_gp_restore 13, $a0 256 fpu_gp_restore 14, $a0 257 fpu_gp_restore 15, $a0 258 fpu_gp_restore 16, $a0 259 fpu_gp_restore 17, $a0 260 fpu_gp_restore 18, $a0 261 fpu_gp_restore 19, $a0 262 fpu_gp_restore 20, $a0 263 fpu_gp_restore 21, $a0 264 fpu_gp_restore 22, $a0 265 fpu_gp_restore 23, $a0 266 fpu_gp_restore 24, $a0 267 fpu_gp_restore 25, $a0 268 fpu_gp_restore 26, $a0 269 fpu_gp_restore 27, $a0 270 fpu_gp_restore 28, $a0 271 fpu_gp_restore 29, $a0 272 fpu_gp_restore 30, $a0 273 fpu_gp_restore 31, $a0 274 275 fpu_ct_restore 1, $a0 276 fpu_ct_restore 2, $a0 277 fpu_ct_restore 3, $a0 278 fpu_ct_restore 4, $a0 279 fpu_ct_restore 5, $a0 280 fpu_ct_restore 6, $a0 281 fpu_ct_restore 7, $a0 282 fpu_ct_restore 8, $a0 283 fpu_ct_restore 9, $a0 284 fpu_ct_restore 10, $a0 285 fpu_ct_restore 11, $a0 286 fpu_ct_restore 12, $a0 287 fpu_ct_restore 13, $a0 288 fpu_ct_restore 14, $a0 289 fpu_ct_restore 15, $a0 290 fpu_ct_restore 16, $a0 291 fpu_ct_restore 17, $a0 292 fpu_ct_restore 18, $a0 293 fpu_ct_restore 19, $a0 294 fpu_ct_restore 20, $a0 295 fpu_ct_restore 21, $a0 296 fpu_ct_restore 22, $a0 297 fpu_ct_restore 23, $a0 298 fpu_ct_restore 24, $a0 299 fpu_ct_restore 25, $a0 300 fpu_ct_restore 26, $a0 301 fpu_ct_restore 27, $a0 302 fpu_ct_restore 28, $a0 303 fpu_ct_restore 29, $a0 304 fpu_ct_restore 30, $a0 305 fpu_ct_restore 31, $a0 306 #endif 304 307 j $ra 305 308 nop
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