Changeset 4d2dba7 in mainline for kernel/genarch/src/drivers/grlib_uart/grlib_uart.c
- Timestamp:
- 2013-10-15T17:05:26Z (11 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- f988a13
- Parents:
- a73ebf0
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/genarch/src/drivers/grlib_uart/grlib_uart.c
ra73ebf0 r4d2dba7 50 50 static void grlib_uart_sendb(outdev_t *dev, uint8_t byte) 51 51 { 52 uint32_t reg; 52 53 grlib_uart_status_t *status; 53 54 grlib_uart_t *uart = … … 56 57 /* Wait for space becoming available in Tx FIFO. */ 57 58 do { 58 status = pio_read_32(&uart->io->status); 59 reg = pio_read_32(&uart->io->status); 60 status = (grlib_uart_status_t *)® 59 61 } while (status->tf != 0); 60 62 … … 85 87 static void grlib_uart_irq_handler(irq_t *irq) 86 88 { 89 uint32_t reg; 87 90 grlib_uart_t *uart = irq->instance; 88 grlib_ status_tstatus;91 grlib_uart_status_t *status; 89 92 90 status = (grlib_status_t)pio_read_32(&uart->io->status); 93 reg = pio_read_32(&uart->io->status); 94 status = (grlib_uart_status_t *)® 91 95 92 96 while (status->dr != 0) { 93 97 uint32_t data = pio_read_32(&uart->io->data); 94 status = (grlib_status_t)pio_read_32(&uart->io->status); 98 reg = pio_read_32(&uart->io->status); 99 status = (grlib_uart_status_t *)® 95 100 indev_push_character(uart->indev, data & 0xff); 96 101 } … … 131 136 132 137 /* Enable FIFO, Tx trigger level: empty, Rx trigger level: 1 byte. */ 133 grlib_ control_t control =138 grlib_uart_control_t control = 134 139 { .fa = 1, .rf = 1, .tf = 1, .ri = 1, 135 140 .te = 1, .re = 1}; 136 141 137 pio_write_32(&uart->io->control, control); 142 uint32_t *reg = (uint32_t *)&control; 143 pio_write_32(&uart->io->control, *reg); 138 144 139 145 link_initialize(&uart->parea.link);
Note:
See TracChangeset
for help on using the changeset viewer.