Changeset 4c754f6 in mainline for kernel/arch/arm32/src/mach/beaglebone/beaglebone.c
- Timestamp:
- 2013-02-11T22:55:29Z (11 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 0f66886
- Parents:
- 40762c6
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
kernel/arch/arm32/src/mach/beaglebone/beaglebone.c
r40762c6 r4c754f6 1 1 /* 2 2 * Copyright (c) 2012 Matteo Facchinetti 3 * Copyright (c) 2012 Maurizio Lombardi 3 4 * All rights reserved. 4 5 * … … 38 39 #include <genarch/drivers/am335x/uart.h> 39 40 #include <genarch/drivers/am335x/timer.h> 41 #include <genarch/drivers/am335x/cm_per.h> 42 #include <genarch/drivers/am335x/cm_dpll.h> 43 #include <genarch/drivers/am335x/ctrl_module.h> 40 44 #include <genarch/srln/srln.h> 41 45 #include <interrupt.h> … … 60 64 static struct beaglebone { 61 65 am335x_irc_regs_t *irc_addr; 66 am335x_cm_per_regs_t *cm_per_addr; 67 am335x_cm_dpll_regs_t *cm_dpll_addr; 68 am335x_ctrl_module_t *ctrl_module; 62 69 am335x_timer_t timer; 63 70 am335x_uart_t uart; … … 79 86 static void bbone_init(void) 80 87 { 81 /* Initialize the interrupt controller */82 88 bbone.irc_addr = (void *) km_map(AM335x_IRC_BASE_ADDRESS, 83 89 AM335x_IRC_SIZE, PAGE_NOT_CACHEABLE); 84 90 91 bbone.cm_per_addr = (void *) km_map(AM335x_CM_PER_BASE_ADDRESS, 92 AM335x_CM_PER_SIZE, PAGE_NOT_CACHEABLE); 93 94 bbone.cm_dpll_addr = (void *) km_map(AM335x_CM_DPLL_BASE_ADDRESS, 95 AM335x_CM_DPLL_SIZE, PAGE_NOT_CACHEABLE); 96 97 bbone.ctrl_module = (void *) km_map(AM335x_CTRL_MODULE_BASE_ADDRESS, 98 AM335x_CTRL_MODULE_SIZE, PAGE_NOT_CACHEABLE); 99 100 /* Initialize the interrupt controller */ 85 101 am335x_irc_init(bbone.irc_addr); 86 102 } … … 105 121 irq_initialize(&timer_irq); 106 122 timer_irq.devno = device_assign_devno(); 107 timer_irq.inr = AM335x_DMTIMER 0_IRQ;123 timer_irq.inr = AM335x_DMTIMER2_IRQ; 108 124 timer_irq.claim = bbone_timer_irq_claim; 109 125 timer_irq.handler = bbone_timer_irq_handler; 110 126 irq_register(&timer_irq); 111 127 112 /* Initialize the DMTIMER0 */ 113 am335x_timer_init(&bbone.timer, DMTIMER0, HZ); 128 /* Enable the DMTIMER2 clock module */ 129 am335x_clock_module_enable(bbone.cm_per_addr, DMTIMER2); 130 /* Select the SYSCLK as the clock source for the dmtimer2 module */ 131 am335x_clock_source_select(bbone.cm_dpll_addr, DMTIMER2, 132 CLK_SRC_M_OSC); 133 /* Initialize the DMTIMER2 */ 134 am335x_timer_init(&bbone.timer, DMTIMER2, HZ, 135 am335x_ctrl_module_clock_freq_get(bbone.ctrl_module)); 114 136 /* Enable the interrupt */ 115 am335x_irc_enable(bbone.irc_addr, AM335x_DMTIMER 0_IRQ);137 am335x_irc_enable(bbone.irc_addr, AM335x_DMTIMER2_IRQ); 116 138 /* Start the timer */ 117 139 am335x_timer_start(&bbone.timer);
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