Changeset 4bd3f45 in mainline

Timestamp:

2012-09-18T13:55:55Z (12 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

1a1b05b

Parents:

f94b95b1

Message:

arm32: Consolidate control register values

Location:

kernel/arch/arm32

Files:

• include/regutils.h (modified) (1 diff)
• src/cpu/cpu.c (modified) (1 diff)
• src/exception.c (modified) (1 diff)

kernel/arch/arm32/include/regutils.h

@@ -41 +41 @@
 #define STATUS_REG_MODE_MASK         0x1f
 
-#define CP15_R1_MMU_ENABLE_BIT       (1 << 0)
-#define CP15_R1_ALIGNMENT_ENABLE_BIT (1 << 1)
-#define CP15_R1_CACHE_ENABLE_BIT     (1 << 2)
-#define CP15_R1_BRANCH_PREDICT_BIT   (1 << 11)
-#define CP15_R1_INST_CACHE_BIT       (1 << 12)
-#define CP15_R1_HIGH_VECTORS_BIT     (1 << 13)
-#define CP15_R1_ROUND_ROBIN_BIT      (1 << 14)
-#define CP15_R1_HA_ENABLE_BIT        (1 << 17)
-#define CP15_R1_WXN_BIT              (1 << 19) /* Only if virt. supported */
-#define CP15_R1_UWXN_BIT             (1 << 20) /* Only if virt. supported */
-#define CP15_R1_FI_BIT               (1 << 21)
-#define CP15_R1_VE_BIT               (1 << 24)
-#define CP15_R1_EE_BIT               (1 << 25)
-#define CP15_R1_NMFI_BIT             (1 << 27)
-#define CP15_R1_TRE_BIT              (1 << 28)
-#define CP15_R1_AFE_BIT              (1 << 29)
+/* COntrol register bit values see ch. B4.1.130 of ARM Architecture Reference
+ * Manual ARMv7-A and ARMv7-R edition, page 1687 */
+#define CP15_R1_MMU_EN            (1 << 0)
+#define CP15_R1_ALIGN_CHECK_EN    (1 << 1)  /* Allow alignemnt check */
+#define CP15_R1_CACHE_EN          (1 << 2)
+#define CP15_R1_CP15_BARRIER_EN   (1 << 5)
+#define CP15_R1_B_EN              (1 << 7)  /* ARMv6- only big endian switch */
+#define CP15_R1_SWAP_EN           (1 << 10)
+#define CP15_R1_BRANCH_PREDICT_EN (1 << 11)
+#define CP15_R1_INST_CACHE_EN     (1 << 12)
+#define CP15_R1_HIGH_VECTORS_EN   (1 << 13)
+#define CP15_R1_ROUND_ROBIN_EN    (1 << 14)
+#define CP15_R1_HW_ACCESS_FLAG_EN (1 << 17)
+#define CP15_R1_WRITE_XN_EN       (1 << 19) /* Only if virt. supported */
+#define CP15_R1_USPCE_WRITE_XN_EN (1 << 20) /* Only if virt. supported */
+#define CP15_R1_FAST_IRQ_EN       (1 << 21) /* Disbale impl.specific features */
+#define CP15_R1_UNALIGNED_EN      (1 << 22) /* Must be 1 on armv7 */
+#define CP15_R1_IRQ_VECTORS_EN    (1 << 24)
+#define CP15_R1_BIG_ENDIAN_EXC    (1 << 25)
+#define CP15_R1_NMFI_EN           (1 << 27)
+#define CP15_R1_TEX_REMAP_EN      (1 << 28)
+#define CP15_R1_ACCESS_FLAG_EN    (1 << 29)
+#define CP15_r1_THUMB_EXC_EN      (1 << 30)
 
 /* ARM Processor Operation Modes */

kernel/arch/arm32/src/cpu/cpu.c

@@ -108 +108 @@
         
         /* Turn off tex remap */
-        control_reg &= ~CP15_R1_TRE_BIT;
+        control_reg &= ~CP15_R1_TEX_REMAP_EN;
         /* Turn off accessed flag */
-        control_reg &= ~(CP15_R1_AFE_BIT | CP15_R1_HA_ENABLE_BIT | CP15_R1_ALIGNMENT_ENABLE_BIT);
+        control_reg &= ~(CP15_R1_ACCESS_FLAG_EN | CP15_R1_HW_ACCESS_FLAG_EN);
+        /* Enable unaligned access (U bit is armv6 only) */
+        control_reg |= CP15_R1_UNALIGNED_EN;
+        /* Disable alignment checks */
+        control_reg &= ~CP15_R1_ALIGN_CHECK_EN;
         /* Enable caching */
-        control_reg |= CP15_R1_CACHE_ENABLE_BIT;
+        control_reg |= CP15_R1_CACHE_EN;
         
         asm volatile (

kernel/arch/arm32/src/exception.c

@@ -143 +143 @@
         
         /* switch on the high vectors bit */
-        control_reg |= CP15_R1_HIGH_VECTORS_BIT;
+        control_reg |= CP15_R1_HIGH_VECTORS_EN;
         
         asm volatile (