Changeset 34847e2 in mainline

Timestamp:

2013-08-15T09:42:40Z (11 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

2921602

Parents:

e93bb24

Message:

arm32: Up to 8 levels of cache are possible

File:

• kernel/arch/arm32/src/cpu/cpu.c (modified) (1 diff)

kernel/arch/arm32/src/cpu/cpu.c

@@ -241 +241 @@
 #ifdef PROCESSOR_ARCH_armv7_a
         const uint32_t val = CLIDR_read();
-        for (unsigned i = 0; i < 7; ++i) {
+        for (unsigned i = 0; i < 8; ++i) {
                 const unsigned ctype = CLIDR_CACHE(i, val);
                 switch (ctype) {