Changeset 23b7c02 in mainline for kernel/arch/arm32/include/arch/mm/page.h

Timestamp:

2013-09-04T06:58:57Z (11 years ago)

Author:

Manuele Conti <conti.ma@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

7664469

Parents:

caf5382 (diff), aa2a049 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.

Message:

Merge with Mainline changes.

File:

• kernel/arch/arm32/include/arch/mm/page.h (modified) (4 diffs)

kernel/arch/arm32/include/arch/mm/page.h

@@ -41 +41 @@
 #include <arch/exception.h>
 #include <arch/barrier.h>
+#include <arch/cp15.h>
 #include <trace.h>
 
@@ -95 +96 @@
 /* Set PTE address accessors for each level. */
 #define SET_PTL0_ADDRESS_ARCH(ptl0) \
-        (set_ptl0_addr((pte_t *) (ptl0)))
+        set_ptl0_addr((pte_t *) (ptl0))
 #define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
-        (((pte_t *) (ptl0))[(i)].l0.coarse_table_addr = (a) >> 10)
+        set_ptl1_addr((pte_t*) (ptl0), i, a)
 #define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
 #define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
 #define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
-        (((pte_t *) (ptl3))[(i)].l1.frame_base_addr = (a) >> 12)
+        set_ptl3_addr((pte_t*) (ptl3), i, a)
 
 /* Get PTE flags accessors for each level. */
@@ -129 +130 @@
         set_pt_level1_present((pte_t *) (ptl3), (size_t) (i))
 
+
+#define pt_coherence(page) pt_coherence_m(page, 1)
+
 #if defined(PROCESSOR_ARCH_armv6) | defined(PROCESSOR_ARCH_armv7_a)
 #include "page_armv6.h"
@@ -137 +141 @@
 #endif
 
+/** Sets the address of level 0 page table.
+ *
+ * @param pt Pointer to the page table to set.
+ *
+ * Page tables are always in cacheable memory.
+ * Make sure the memory type is correct, and in sync with:
+ * init_boot_pt (boot/arch/arm32/src/mm.c)
+ * init_ptl0_section (boot/arch/arm32/src/mm.c)
+ * set_pt_level1_flags (kernel/arch/arm32/include/arch/mm/page_armv6.h)
+ */
+NO_TRACE static inline void set_ptl0_addr(pte_t *pt)
+{
+        uint32_t val = (uint32_t)pt & TTBR_ADDR_MASK;
+        val |= TTBR_RGN_WBWA_CACHE | TTBR_C_FLAG;
+        TTBR0_write(val);
+}
+
+NO_TRACE static inline void set_ptl1_addr(pte_t *pt, size_t i, uintptr_t address)
+{
+        pt[i].l0.coarse_table_addr = address >> 10;
+        pt_coherence(&pt[i].l0);
+}
+
+NO_TRACE static inline void set_ptl3_addr(pte_t *pt, size_t i, uintptr_t address)
+{
+        pt[i].l1.frame_base_addr = address >> 12;
+        pt_coherence(&pt[i].l1);
+}
+
 #endif