Changeset 1a3a632 in mainline

Timestamp:

2013-01-01T11:48:19Z (11 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

0acd339

Parents:

4a46ccc

Message:

arm32, boot: Merge Cortex-A8 and gta02 paths.

We enable caches and branch prediction on both.

File:

• boot/arch/arm32/src/mm.c (modified) (2 diffs)

boot/arch/arm32/src/mm.c

@@ -142 +142 @@
                 "mrc p15, 0, r0, c1, c0, 0\n"
                 
-#ifdef PROCESSOR_cortex_a8
+#if defined(PROCESSOR_cortex_a8) | defined(MACHINE_gta02)
                 /* Mask to enable paging, I-cache D-cache and branch predict
                  * See kernel/arch/arm32/include/regutils.h for bit values.
                  * It's safe because Cortex-A8 implements IVIPT extension
-                 * See Cortex-A8 TRM ch. 7.2.6 p. 7-4 (PDF 245) */
+                 * See Cortex-A8 TRM ch. 7.2.6 p. 7-4 (PDF 245).
+                 * It's safe for gta02 too because we turn the caches off
+                 * before switching to kernel. */
                 "ldr r1, =0x00001805\n"
 #elif defined(PROCESSOR_ARCH_armv7_a) | defined(PROCESSOR_ARCH_armv6)
@@ -152 +154 @@
                  * see arch/arm32/src/cpu/cpu.c for reasoning */
                 "ldr r1, =0x00000805\n"
-#elif defined(MACHINE_gta02)
-                /* Mask to enable paging (bit 0),
-                   D-cache (bit 2), I-cache (bit 12) */
-                "ldr r1, =0x00001005\n"
 #else
                 /* Mask to enable paging and branch prediction */