Changeset 19acf24 in mainline for uspace/drv/infrastructure/rootamdm37x/cm/clock_control.h

Timestamp:

2012-11-20T13:42:00Z (11 years ago)

Author:

Jan Vesely <jano.vesely@…>

Branches:

lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export

Children:

bf6f6ca

Parents:

9c0eba6

Message:

rootamdm37x: Print Core clock and l3 interface clock values.

File:

• uspace/drv/infrastructure/rootamdm37x/cm/clock_control.h (modified) (1 diff)

uspace/drv/infrastructure/rootamdm37x/cm/clock_control.h

@@ -114 +114 @@
         ioport32_t clksel1_pll;
 #define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_MASK   (0x1f << 27)
-#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_(x)   (((x) & 0x1f) << 27)
+#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_CREATE(x)   (((x) & 0x1f) << 27)
+#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_CLKOUT_DIV_GET(x)   (((x) >> 27) & 0x1f)
 #define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_MASK   (0x7ff << 16)
-#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT(x)   (((x) & 0x7ff) << 16)
+#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_CREATE(x)   (((x) & 0x7ff) << 16)
+#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_MULT_GET(x)   (((x) >> 16) & 0x7ff)
 #define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_MASK   (0x7f << 8)
-#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV(x)   (((x) & 0x7f) << 8)
+#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_CREATE(x)   (((x) & 0x7f) << 8)
+#define CLOCK_CONTROL_CM_CLKSEL1_PLL_CORE_DPLL_DIV_GET(x)   (((x) >> 8) & 0x7f)
 #define CLOCK_CONTROL_CM_CLKSEL1_PLL_SOURCE_96M_FLAG   (1 << 6)
 #define CLOCK_CONTROL_CM_CLKSEL1_PLL_SOURCE_54M_FLAG   (1 << 5)