Changeset 17aca1c in mainline for kernel/arch/mips32/src/mm/tlb.c


Ignore:
Timestamp:
2011-02-04T20:56:52Z (13 years ago)
Author:
Vojtech Horky <vojtechhorky@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
0397e5a4, e29e09cf
Parents:
e778543 (diff), 0b37882 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge mainline changes

File:
1 edited

Legend:

Unmodified
Added
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  • kernel/arch/mips32/src/mm/tlb.c

    re778543 r17aca1c  
    557557        entry_hi_t hi, hi_save;
    558558        tlb_index_t index;
    559 
    560         ASSERT(asid != ASID_INVALID);
     559       
     560        if (asid == ASID_INVALID)
     561                return;
    561562
    562563        hi_save.value = cp0_entry_hi_read();
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