Changeset 15d0046 in mainline for uspace/drv/char/pl050/pl050_hw.h


Ignore:
Timestamp:
2014-09-12T13:22:33Z (11 years ago)
Author:
Vojtech Horky <vojtechhorky@…>
Branches:
lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
Children:
9b20126
Parents:
8db09e4 (diff), 105d8d6 (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the (diff) links above to see all the changes relative to each parent.
Message:

Merge mainline changes

File:
1 moved

Legend:

Unmodified
Added
Removed

  • uspace/drv/char/pl050/pl050_hw.h

    r8db09e4 r15d0046  
    11/*
    2  * Copyright (c) 2006 Ondrej Palkovsky
     2 * Copyright (c) 2009 Vineeth Pillai
     3 * Copyright (c) 2014 Jiri Svoboda
    34 * All rights reserved.
    45 *
    … …  
    2728 */
    2829
    29 /** @addtogroup libcmips64
     30/** @addtogroup pl050
    3031 * @{
    3132 */
    32 /** @file
    33  * @ingroup libcmips64
     33/** @file ARM PrimeCell PS2 Keyboard/Mouse Interface (PL050) registers
    3434 */
    3535
    36 #ifndef LIBC_mips64_FIBRIL_H_
    37 #define LIBC_mips64_FIBRIL_H_
     36#ifndef PL050_HW_H
     37#define PL050_HW_H
    3838
    3939#include <sys/types.h>
    40 #include <libarch/stack.h>
    41 #include <align.h>
    42 
    43 #define SP_DELTA  (ABI_STACK_FRAME + ALIGN_UP(STACK_ITEM_SIZE, STACK_ALIGNMENT))
    44 
    45 /*
    46  * We define our own context_set, because we need to set
    47  * the TLS pointer to the tcb + 0x7000
    48  *
    49  * See tls_set in thread.h
    50  */
    51 #define context_set(c, _pc, stack, size, ptls) \
    52         do { \
    53                 (c)->pc = (sysarg_t) (_pc); \
    54                 (c)->sp = ((sysarg_t) (stack)) + (size) - SP_DELTA; \
    55                 (c)->tls = ((sysarg_t)(ptls)) + 0x7000 + sizeof(tcb_t); \
    56         } while (0)
    5740
    5841typedef struct {
    59         uint64_t sp;
    60         uint64_t pc;
    61        
    62         uint64_t s0;
    63         uint64_t s1;
    64         uint64_t s2;
    65         uint64_t s3;
    66         uint64_t s4;
    67         uint64_t s5;
    68         uint64_t s6;
    69         uint64_t s7;
    70         uint64_t s8;
    71         uint64_t gp;
    72         uint64_t tls; /* Thread local storage (k1) */
    73        
    74         uint64_t f20;
    75         uint64_t f21;
    76         uint64_t f22;
    77         uint64_t f23;
    78         uint64_t f24;
    79         uint64_t f25;
    80         uint64_t f26;
    81         uint64_t f27;
    82         uint64_t f28;
    83         uint64_t f29;
    84         uint64_t f30;
    85 } context_t;
     42        /** Control register */
     43        uint8_t cr;
     44        /** Padding */
     45        uint8_t pad1[3];
     46        /** Status register */
     47        uint8_t stat;
     48        /** Padding */
     49        uint8_t pad5[3];
     50        /** Received data */
     51        uint8_t data;
     52        /** Padding */
     53        uint8_t pad9[3];
     54        /** Clock divisor */
     55        uint8_t clkdiv;
     56        /** Padding */
     57        uint8_t pad13[3];
     58        /** Interrupt status register */
     59        uint8_t ir;
     60        /** Padding */
     61        uint8_t pad17[3];
     62} kmi_regs_t;
    8663
    87 static inline uintptr_t context_get_fp(context_t *ctx)
    88 {
    89         return ctx->sp;
    90 }
     64typedef enum {
     65        /** 0 = PS2 mode, 1 = No line control bit mode */
     66        kmi_cr_type = 5,
     67        /** Enable receiver interrupt */
     68        kmi_cr_rxintr = 4,
     69        /** Enable transmitter interrupt */
     70        kmi_cr_txintr = 3,
     71        /** Enable PrimeCell KMI */
     72        kmi_cr_enable = 2,
     73        /** Force KMI data LOW */
     74        kmi_cr_forcedata = 1,
     75        /** Force KMI clock LOW */
     76        kmi_cr_forceclock = 0
     77} kmi_cr_bits_t;
     78
     79typedef enum {
     80        kmi_stat_txempty = 6,
     81        kmi_stat_txbusy = 5,
     82        kmi_stat_rxfull = 4,
     83        kmi_stat_rxbusy = 3,
     84        kmi_stat_rxparity = 2,
     85        kmi_stat_clkin = 1,
     86        kmi_stat_datain = 0
     87} kmi_stat_bits_t;
    9188
    9289#endif
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