Changeset 0b749a3 in mainline for kernel/arch/mips32/src/start.S
- Timestamp:
- 2010-11-22T15:39:53Z (13 years ago)
- Branches:
- lfn, master, serial, ticket/834-toolchain-update, topic/msim-upgrade, topic/simplify-dev-export
- Children:
- 0eddb76, aae339e9
- Parents:
- 9a1d8ab (diff), 8cd1aa5e (diff)
Note: this is a merge changeset, the changes displayed below correspond to the merge itself.
Use the(diff)links above to see all the changes relative to each parent. - File:
-
- 1 edited
-
kernel/arch/mips32/src/start.S (modified) (13 diffs)
Legend:
- Unmodified
- Added
- Removed
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kernel/arch/mips32/src/start.S
r9a1d8ab r0b749a3 46 46 47 47 /* 48 * Which status bits shouldare thread-local:48 * Which status bits are thread-local: 49 49 * KSU(UM), EXL, ERL, IE 50 50 */ 51 51 #define REG_SAVE_MASK 0x1f 52 53 #define ISTATE_OFFSET_A0 0 54 #define ISTATE_OFFSET_A1 4 55 #define ISTATE_OFFSET_A2 8 56 #define ISTATE_OFFSET_A3 12 57 #define ISTATE_OFFSET_T0 16 58 #define ISTATE_OFFSET_T1 20 59 #define ISTATE_OFFSET_V0 24 60 #define ISTATE_OFFSET_V1 28 61 #define ISTATE_OFFSET_AT 32 62 #define ISTATE_OFFSET_T2 36 63 #define ISTATE_OFFSET_T3 40 64 #define ISTATE_OFFSET_T4 44 65 #define ISTATE_OFFSET_T5 48 66 #define ISTATE_OFFSET_T6 52 67 #define ISTATE_OFFSET_T7 56 68 #define ISTATE_OFFSET_S0 60 69 #define ISTATE_OFFSET_S1 64 70 #define ISTATE_OFFSET_S2 68 71 #define ISTATE_OFFSET_S3 72 72 #define ISTATE_OFFSET_S4 76 73 #define ISTATE_OFFSET_S5 80 74 #define ISTATE_OFFSET_S6 84 75 #define ISTATE_OFFSET_S7 88 76 #define ISTATE_OFFSET_T8 92 77 #define ISTATE_OFFSET_T9 96 78 #define ISTATE_OFFSET_KT0 100 79 #define ISTATE_OFFSET_KT1 104 80 #define ISTATE_OFFSET_GP 108 81 #define ISTATE_OFFSET_SP 112 82 #define ISTATE_OFFSET_S8 116 83 #define ISTATE_OFFSET_RA 120 84 #define ISTATE_OFFSET_LO 124 85 #define ISTATE_OFFSET_HI 128 86 #define ISTATE_OFFSET_STATUS 132 87 #define ISTATE_OFFSET_EPC 136 88 #define ISTATE_OFFSET_ALIGNMENT 140 89 90 #define ISTATE_SOFT_SIZE 144 91 92 /* 93 * The fake ABI prologue is never executed and may not be part of the 94 * procedure's body. Instead, it should be immediately preceding the procedure's 95 * body. Its only purpose is to trick the stack trace walker into thinking that 96 * the exception is more or less just a normal function call. 97 */ 98 .macro FAKE_ABI_PROLOGUE 99 sub $sp, ISTATE_SOFT_SIZE 100 sw $ra, ISTATE_OFFSET_EPC($sp) 101 .endm 52 102 53 103 /* … … 58 108 */ 59 109 .macro REGISTERS_STORE_AND_EXC_RESET r 60 sw $at, EOFFSET_AT(\r) 61 sw $v0, EOFFSET_V0(\r) 62 sw $v1, EOFFSET_V1(\r) 63 sw $a0, EOFFSET_A0(\r) 64 sw $a1, EOFFSET_A1(\r) 65 sw $a2, EOFFSET_A2(\r) 66 sw $a3, EOFFSET_A3(\r) 67 sw $t0, EOFFSET_T0(\r) 68 sw $t1, EOFFSET_T1(\r) 69 sw $t2, EOFFSET_T2(\r) 70 sw $t3, EOFFSET_T3(\r) 71 sw $t4, EOFFSET_T4(\r) 72 sw $t5, EOFFSET_T5(\r) 73 sw $t6, EOFFSET_T6(\r) 74 sw $t7, EOFFSET_T7(\r) 75 sw $t8, EOFFSET_T8(\r) 76 sw $t9, EOFFSET_T9(\r) 110 sw $at, ISTATE_OFFSET_AT(\r) 111 sw $v0, ISTATE_OFFSET_V0(\r) 112 sw $v1, ISTATE_OFFSET_V1(\r) 113 sw $a0, ISTATE_OFFSET_A0(\r) 114 sw $a1, ISTATE_OFFSET_A1(\r) 115 sw $a2, ISTATE_OFFSET_A2(\r) 116 sw $a3, ISTATE_OFFSET_A3(\r) 117 sw $t0, ISTATE_OFFSET_T0(\r) 118 sw $t1, ISTATE_OFFSET_T1(\r) 119 sw $t2, ISTATE_OFFSET_T2(\r) 120 sw $t3, ISTATE_OFFSET_T3(\r) 121 sw $t4, ISTATE_OFFSET_T4(\r) 122 sw $t5, ISTATE_OFFSET_T5(\r) 123 sw $t6, ISTATE_OFFSET_T6(\r) 124 sw $t7, ISTATE_OFFSET_T7(\r) 125 sw $t8, ISTATE_OFFSET_T8(\r) 126 sw $t9, ISTATE_OFFSET_T9(\r) 127 sw $s0, ISTATE_OFFSET_S0(\r) 128 sw $s1, ISTATE_OFFSET_S1(\r) 129 sw $s2, ISTATE_OFFSET_S2(\r) 130 sw $s3, ISTATE_OFFSET_S3(\r) 131 sw $s4, ISTATE_OFFSET_S4(\r) 132 sw $s5, ISTATE_OFFSET_S5(\r) 133 sw $s6, ISTATE_OFFSET_S6(\r) 134 sw $s7, ISTATE_OFFSET_S7(\r) 135 sw $s8, ISTATE_OFFSET_S8(\r) 77 136 78 137 mflo $at 79 sw $at, EOFFSET_LO(\r)138 sw $at, ISTATE_OFFSET_LO(\r) 80 139 mfhi $at 81 sw $at, EOFFSET_HI(\r) 82 83 sw $gp, EOFFSET_GP(\r) 84 sw $ra, EOFFSET_RA(\r) 85 sw $k1, EOFFSET_K1(\r) 140 sw $at, ISTATE_OFFSET_HI(\r) 141 142 sw $gp, ISTATE_OFFSET_GP(\r) 143 sw $ra, ISTATE_OFFSET_RA(\r) 144 sw $k0, ISTATE_OFFSET_KT0(\r) 145 sw $k1, ISTATE_OFFSET_KT1(\r) 86 146 87 147 mfc0 $t0, $status … … 95 155 and $t0, $t0, $t3 96 156 97 sw $t2, EOFFSET_STATUS(\r)98 sw $t1, EOFFSET_EPC(\r)157 sw $t2, ISTATE_OFFSET_STATUS(\r) 158 sw $t1, ISTATE_OFFSET_EPC(\r) 99 159 mtc0 $t0, $status 100 160 .endm … … 106 166 */ 107 167 mfc0 $t0, $status 108 lw $t1, EOFFSET_STATUS(\r)168 lw $t1, ISTATE_OFFSET_STATUS(\r) 109 169 110 170 /* mask UM, EXL, ERL, IE */ … … 116 176 mtc0 $t0, $status 117 177 118 lw $v0, EOFFSET_V0(\r)119 lw $v1, EOFFSET_V1(\r)120 lw $a0, EOFFSET_A0(\r)121 lw $a1, EOFFSET_A1(\r)122 lw $a2, EOFFSET_A2(\r)123 lw $a3, EOFFSET_A3(\r)124 lw $t0, EOFFSET_T0(\r)125 lw $t1, EOFFSET_T1(\r)126 lw $t2, EOFFSET_T2(\r)127 lw $t3, EOFFSET_T3(\r)128 lw $t4, EOFFSET_T4(\r)129 lw $t5, EOFFSET_T5(\r)130 lw $t6, EOFFSET_T6(\r)131 lw $t7, EOFFSET_T7(\r)132 lw $t8, EOFFSET_T8(\r)133 lw $t9, EOFFSET_T9(\r)134 135 lw $gp, EOFFSET_GP(\r)136 lw $ra, EOFFSET_RA(\r)137 lw $k1, EOFFSET_K1(\r)138 139 lw $at, EOFFSET_LO(\r)178 lw $v0, ISTATE_OFFSET_V0(\r) 179 lw $v1, ISTATE_OFFSET_V1(\r) 180 lw $a0, ISTATE_OFFSET_A0(\r) 181 lw $a1, ISTATE_OFFSET_A1(\r) 182 lw $a2, ISTATE_OFFSET_A2(\r) 183 lw $a3, ISTATE_OFFSET_A3(\r) 184 lw $t0, ISTATE_OFFSET_T0(\r) 185 lw $t1, ISTATE_OFFSET_T1(\r) 186 lw $t2, ISTATE_OFFSET_T2(\r) 187 lw $t3, ISTATE_OFFSET_T3(\r) 188 lw $t4, ISTATE_OFFSET_T4(\r) 189 lw $t5, ISTATE_OFFSET_T5(\r) 190 lw $t6, ISTATE_OFFSET_T6(\r) 191 lw $t7, ISTATE_OFFSET_T7(\r) 192 lw $t8, ISTATE_OFFSET_T8(\r) 193 lw $t9, ISTATE_OFFSET_T9(\r) 194 195 lw $gp, ISTATE_OFFSET_GP(\r) 196 lw $ra, ISTATE_OFFSET_RA(\r) 197 lw $k1, ISTATE_OFFSET_KT1(\r) 198 199 lw $at, ISTATE_OFFSET_LO(\r) 140 200 mtlo $at 141 lw $at, EOFFSET_HI(\r)201 lw $at, ISTATE_OFFSET_HI(\r) 142 202 mthi $at 143 203 144 lw $at, EOFFSET_EPC(\r)204 lw $at, ISTATE_OFFSET_EPC(\r) 145 205 mtc0 $at, $epc 146 206 147 lw $at, EOFFSET_AT(\r)148 lw $sp, EOFFSET_SP(\r)207 lw $at, ISTATE_OFFSET_AT(\r) 208 lw $sp, ISTATE_OFFSET_SP(\r) 149 209 .endm 150 210 … … 159 219 160 220 beq $k0, $0, 1f 161 add $k0, $sp, 0221 move $k0, $sp 162 222 163 223 /* move $k0 pointer to kernel stack */ … … 166 226 167 227 /* move $k0 (supervisor_sp) */ 168 lw $k0, 0($k0)228 lw $k0, ($k0) 169 229 170 230 1: … … 202 262 nop 203 263 264 FAKE_ABI_PROLOGUE 204 265 exception_handler: 205 266 KERNEL_STACK_TO_K0 206 267 207 sub $k0, REGISTER_SPACE208 sw $sp, EOFFSET_SP($k0)268 sub $k0, ISTATE_SOFT_SIZE 269 sw $sp, ISTATE_OFFSET_SP($k0) 209 270 move $sp, $k0 210 271 … … 227 288 /* the $sp is automatically restored to former value */ 228 289 eret 229 230 #define SS_SP EOFFSET_SP231 #define SS_STATUS EOFFSET_STATUS232 #define SS_EPC EOFFSET_EPC233 #define SS_K1 EOFFSET_K1234 290 235 291 /** Syscall entry … … 249 305 */ 250 306 syscall_shortcut: 251 /* we have a lot of space on the stack, with free use */252 307 mfc0 $t3, $epc 253 308 mfc0 $t2, $status 254 sw $t3, SS_EPC($sp) /* save EPC */255 sw $k1, SS_K1($sp)/* save $k1 not saved on context switch */309 sw $t3, ISTATE_OFFSET_EPC($sp) /* save EPC */ 310 sw $k1, ISTATE_OFFSET_KT1($sp) /* save $k1 not saved on context switch */ 256 311 257 312 and $t4, $t2, REG_SAVE_MASK /* save only KSU, EXL, ERL, IE */ … … 260 315 ori $t2, $t2, 0x1 /* set IE */ 261 316 262 sw $t4, SS_STATUS($sp)317 sw $t4, ISTATE_OFFSET_STATUS($sp) 263 318 mtc0 $t2, $status 264 319 265 320 /* 266 321 * Call the higher level system call handler. 267 * We are going to reuse part of the unused exception stack frame.268 322 * 269 323 */ 270 sw $t0, STACK_ARG4($sp) /* save the 5th argument on the stack */271 sw $t1, STACK_ARG5($sp) /* save the 6th argument on the stack */324 sw $t0, ISTATE_OFFSET_T0($sp) /* save the 5th argument on the stack */ 325 sw $t1, ISTATE_OFFSET_T1($sp) /* save the 6th argument on the stack */ 272 326 jal syscall_handler 273 sw $v0, STACK_ARG6($sp) /* save the syscall number on the stack */327 sw $v0, ISTATE_OFFSET_V0($sp) /* save the syscall number on the stack */ 274 328 275 329 /* restore status */ 276 330 mfc0 $t2, $status 277 lw $t3, SS_STATUS($sp)331 lw $t3, ISTATE_OFFSET_STATUS($sp) 278 332 279 333 /* … … 288 342 289 343 /* restore epc + 4 */ 290 lw $t2, SS_EPC($sp)291 lw $k1, SS_K1($sp)344 lw $t2, ISTATE_OFFSET_EPC($sp) 345 lw $k1, ISTATE_OFFSET_KT1($sp) 292 346 addi $t2, $t2, 4 293 347 mtc0 $t2, $epc 294 348 295 lw $sp, SS_SP($sp) /* restore $sp */ 296 eret 297 349 lw $sp, ISTATE_OFFSET_SP($sp) /* restore $sp */ 350 eret 351 352 FAKE_ABI_PROLOGUE 298 353 tlb_refill_handler: 299 354 KERNEL_STACK_TO_K0 300 sub $k0, REGISTER_SPACE355 sub $k0, ISTATE_SOFT_SIZE 301 356 REGISTERS_STORE_AND_EXC_RESET $k0 302 sw $sp, EOFFSET_SP($k0)303 add $sp, $k0,0357 sw $sp, ISTATE_OFFSET_SP($k0) 358 move $sp, $k0 304 359 305 360 jal tlb_refill 306 add $a0, $sp, 0361 move $a0, $sp 307 362 308 363 REGISTERS_LOAD $sp 309 364 eret 310 365 366 FAKE_ABI_PROLOGUE 311 367 cache_error_handler: 312 368 KERNEL_STACK_TO_K0 313 sub $k0, REGISTER_SPACE369 sub $k0, ISTATE_SOFT_SIZE 314 370 REGISTERS_STORE_AND_EXC_RESET $k0 315 sw $sp, EOFFSET_SP($k0)316 add $sp, $k0,0371 sw $sp, ISTATE_OFFSET_SP($k0) 372 move $sp, $k0 317 373 318 374 jal cache_error 319 add $a0, $sp, 0375 move $a0, $sp 320 376 321 377 REGISTERS_LOAD $sp … … 323 379 324 380 userspace_asm: 325 add $sp, $a0,0326 add $v0, $a1, 0327 add $t9, $a2, 0/* set up correct entry into PIC code */381 move $sp, $a0 382 move $v0, $a1 383 move $t9, $a2 /* set up correct entry into PIC code */ 328 384 xor $a0, $a0, $a0 /* $a0 is defined to hold pcb_ptr */ 329 385 /* set it to 0 */
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